A CMOS 6-bit 16-GS/s time-interleaved ADC with digital background calibration

Chun Cheng Huang*, Chung Yi Wang, Jieh-Tsorng Wu

*此作品的通信作者

    研究成果: Conference contribution同行評審

    23 引文 斯高帕斯(Scopus)

    摘要

    An 8-channel 6-bit 16-GS/s time-interleaved ADC was fabricated using a 65nm CMOS technology. Each A/D channel is a flash ADC using latch-type comparator with background offset calibration. Timing skews among the channels are also continuously calibrated in the background. The chip achieves 42.3dB SFDR and 30.8dB SNDR at 16 GS/s sampling rate.

    原文English
    主出版物標題2010 Symposium on VLSI Circuits, VLSIC 2010
    頁面159-160
    頁數2
    DOIs
    出版狀態Published - 22 十月 2010
    事件2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States
    持續時間: 16 六月 201018 六月 2010

    出版系列

    名字IEEE Symposium on VLSI Circuits, Digest of Technical Papers

    Conference

    Conference2010 24th Symposium on VLSI Circuits, VLSIC 2010
    國家/地區United States
    城市Honolulu, HI
    期間16/06/1018/06/10

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