An 8-channel 6-bit 16-GS/s time-interleaved ADC was fabricated using a 65nm CMOS technology. Each A/D channel is a flash ADC using latch-type comparator with background offset calibration. Timing skews among the channels are also continuously calibrated in the background. The chip achieves 42.3dB SFDR and 30.8dB SNDR at 16 GS/s sampling rate.
|主出版物標題||2010 Symposium on VLSI Circuits, VLSIC 2010|
|出版狀態||Published - 22 十月 2010|
|事件||2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States|
持續時間: 16 六月 2010 → 18 六月 2010
|名字||IEEE Symposium on VLSI Circuits, Digest of Technical Papers|
|Conference||2010 24th Symposium on VLSI Circuits, VLSIC 2010|
|期間||16/06/10 → 18/06/10|