A capacitorless double-gate DRAM cell design for high density applications

Charles Kuo; Tsu Jae King; Chen-Ming Hu

doi:10.1109/IEDM.2002.1175969

A capacitorless double-gate DRAM cell design for high density applications

Charles Kuo^*, Tsu Jae King, Chen-Ming Hu

^*此作品的通信作者

國際半導體產業學院

研究成果: Conference article › 同行評審

35 引文斯高帕斯（Scopus）

摘要

Experimental measurements and 2-D device simulation are used to investigate a capacitorless, asymmetric double-gate DRAM (DG-DRAM) design. Soft error problems are discussed. Careful attention to cell geometry and film quality results in intrinsic retention times suitable for stand-alone and embedded memories.

原文	English
頁（從 - 到）	843-846
頁數	4
期刊	Technical Digest - International Electron Devices Meeting
DOIs	https://doi.org/10.1109/IEDM.2002.1175969
出版狀態	Published - 1 12月 2002
事件	2002 IEEE International Devices Meeting (IEDM) - San Francisco, CA, 美國持續時間: 8 12月 2002 → 11 12月 2002

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10.1109/IEDM.2002.1175969

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title = "A capacitorless double-gate DRAM cell design for high density applications",

abstract = "Experimental measurements and 2-D device simulation are used to investigate a capacitorless, asymmetric double-gate DRAM (DG-DRAM) design. Soft error problems are discussed. Careful attention to cell geometry and film quality results in intrinsic retention times suitable for stand-alone and embedded memories.",

author = "Charles Kuo and King, {Tsu Jae} and Chen-Ming Hu",

year = "2002",

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doi = "10.1109/IEDM.2002.1175969",

language = "English",

pages = "843--846",

journal = "Technical Digest - International Electron Devices Meeting",

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T1 - A capacitorless double-gate DRAM cell design for high density applications

AU - Kuo, Charles

AU - King, Tsu Jae

AU - Hu, Chen-Ming

PY - 2002/12/1

Y1 - 2002/12/1

N2 - Experimental measurements and 2-D device simulation are used to investigate a capacitorless, asymmetric double-gate DRAM (DG-DRAM) design. Soft error problems are discussed. Careful attention to cell geometry and film quality results in intrinsic retention times suitable for stand-alone and embedded memories.

AB - Experimental measurements and 2-D device simulation are used to investigate a capacitorless, asymmetric double-gate DRAM (DG-DRAM) design. Soft error problems are discussed. Careful attention to cell geometry and film quality results in intrinsic retention times suitable for stand-alone and embedded memories.

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U2 - 10.1109/IEDM.2002.1175969

DO - 10.1109/IEDM.2002.1175969

M3 - Conference article

AN - SCOPUS:0036932015

SN - 0163-1918

SP - 843

EP - 846

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - 2002 IEEE International Devices Meeting (IEDM)

Y2 - 8 December 2002 through 11 December 2002

ER -

A capacitorless double-gate DRAM cell design for high density applications

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