TY - GEN
T1 - A bending n-well ballast layout to improve esd robustness in fully-silicided CMOS technology
AU - Wen, Yong Ru
AU - Ker, Ming-Dou
AU - Chen, Wen Yi
PY - 2010/10/20
Y1 - 2010/10/20
N2 - Ballast technique has been reported as a cost effective method to improve ESD robustness of fully-silicided devices without using silicide block. In this work, a new ballast technique, the bending N-Well (BNW) ballast structure, is proposed to enhance ESD robustness of fully-silicided NMOS. With a deep N-Well to cover the fully-silicided NMOS with BNW ballast structure, ESD robustness of the NMOS can be further improved by enhancing the turn-on uniformity among the multi-fingers of the NMOS.
AB - Ballast technique has been reported as a cost effective method to improve ESD robustness of fully-silicided devices without using silicide block. In this work, a new ballast technique, the bending N-Well (BNW) ballast structure, is proposed to enhance ESD robustness of fully-silicided NMOS. With a deep N-Well to cover the fully-silicided NMOS with BNW ballast structure, ESD robustness of the NMOS can be further improved by enhancing the turn-on uniformity among the multi-fingers of the NMOS.
UR - http://www.scopus.com/inward/record.url?scp=77957911973&partnerID=8YFLogxK
U2 - 10.1109/IRPS.2010.5488718
DO - 10.1109/IRPS.2010.5488718
M3 - Conference contribution
AN - SCOPUS:77957911973
SN - 9781424454310
T3 - IEEE International Reliability Physics Symposium Proceedings
SP - 857
EP - 860
BT - 2010 IEEE International Reliability Physics Symposium, IRPS 2010
T2 - 2010 IEEE International Reliability Physics Symposium, IRPS 2010
Y2 - 2 May 2010 through 6 May 2010
ER -