A Background Timing-Skew Calibration Technique for Time-Interleaved Analog-to-Digital Converters

Chung Yi Wang, Jieh-Tsorng Wu

研究成果: Article同行評審

38 引文 斯高帕斯(Scopus)

摘要

This paper presents a background timing-skew calibration technique for time-interleaved analog-to-digital converters (ADCs). The timing skew between any two adjacent analog-digital (A/D) channels is detected by counting the number of zero crossings of the ADCs input while randomly alternating their sampling sequence. Digitally controlled delay units are adjusted to minimize the timing skews among the A/D channels caused by the mismatches among the clock routes. The calibration behaviors, including converging speed and timing jitter, are theoretically analyzed and verified with simulations. A 6-bit 16-channel ADC is used as an example.

原文English
頁(從 - 到)299-303
頁數5
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
53
發行號4
DOIs
出版狀態Published - 6 四月 2006

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