A 99.4 dB SFDR 91.9 dB DR Continuous-Time Incremental Delta-Sigma ADC with a Noise-Shaping SAR Quantizer and a Passive Input Feedforward Stabilization Path

Sensor readout system-on-chips (SoCs) have become ubiquitous, demanding high-resolution medium-speed ADCs to multiplex among multiple sensor channels. Incremental δσ ADCs (IADCs) stand out for their superior energy efficiency. Continuous-Time (CT) implementation suffers less from large-signal slewing, and the resistive input mitigates the preceding preamp's driving capability issues. Therefore, CT IADCs can outperform the switched-capacitor counterparts to further improve the energy efficiency of sensor SoCs. To achieve a higher resolution and a better efficiency, digital noise coupling (DNC) is an effective technique to boost the noise-shaping up to 4th-order [1]. Or, hybrid operation combining an IADC and a successive approximation register (SAR) ADC [2] is another alternative. However, 4th-order cascade-of-integrators (Col) digital filter causes much more noise penalty in IADC operation. And, two-step hybrid operation [2] is very sensitive to coefficient matching which demands very stringent requirements for hardware. In addition, the intermittent 'reset' necessary to clear memory during continuous operation degrades CT IADCs' performance, which does not occur in conventional modulators. This paper presents several design techniques and addresses reset-related problems for the design of a high-resolution CT IADC.