In this paper, a high-speed Max-Log MAP decoder is presented for soft-in and soft-out trellis decoding. The high throughput is achieved with a two-dimensional ACS design on the high-radix trellis structure, resulting in a highly parallel and area-efficient decoder. We further apply the retiming technique to reduce the critical path delay of ACS operation. After 0.13μm CMOS chip implementation, the decoder occupies 1.96mm2 area containing 220K gates. The estimated timing under the 1.08V supply and the worst case corner shows that the test chip can achieve the maximum 952MS/S throughput. To our knowledge, the present Max-Log MAP decoder has the highest throughput with the modest hardware cost.
|出版狀態||Published - 1 12月 2006|
|事件||2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China|
持續時間: 13 11月 2006 → 15 11月 2006
|Conference||2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006|
|期間||13/11/06 → 15/11/06|