A 952MS/S max-log MAP decoder chip using radix-4 × 4 ACS architecture

Cheng Hao Tang; Cheng Chi Wong; Chih Lung Chen; Chien Ching Lin; Hsie-Chia Chang

doi:10.1109/ASSCC.2006.357856

A 952MS/S max-log MAP decoder chip using radix-4 × 4 ACS architecture

Cheng Hao Tang^*, Cheng Chi Wong, Chih Lung Chen, Chien Ching Lin, Hsie-Chia Chang

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研究成果: Paper › 同行評審

22 引文斯高帕斯（Scopus）

摘要

In this paper, a high-speed Max-Log MAP decoder is presented for soft-in and soft-out trellis decoding. The high throughput is achieved with a two-dimensional ACS design on the high-radix trellis structure, resulting in a highly parallel and area-efficient decoder. We further apply the retiming technique to reduce the critical path delay of ACS operation. After 0.13μm CMOS chip implementation, the decoder occupies 1.96mm² area containing 220K gates. The estimated timing under the 1.08V supply and the worst case corner shows that the test chip can achieve the maximum 952MS/S throughput. To our knowledge, the present Max-Log MAP decoder has the highest throughput with the modest hardware cost.

原文	English
頁面	79-82
頁數	4
DOIs	https://doi.org/10.1109/ASSCC.2006.357856
出版狀態	Published - 1 12月 2006
事件	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China 持續時間: 13 11月 2006 → 15 11月 2006

Conference

Conference	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
國家/地區	China
城市	Hangzhou
期間	13/11/06 → 15/11/06

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10.1109/ASSCC.2006.357856

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abstract = "In this paper, a high-speed Max-Log MAP decoder is presented for soft-in and soft-out trellis decoding. The high throughput is achieved with a two-dimensional ACS design on the high-radix trellis structure, resulting in a highly parallel and area-efficient decoder. We further apply the retiming technique to reduce the critical path delay of ACS operation. After 0.13μm CMOS chip implementation, the decoder occupies 1.96mm2 area containing 220K gates. The estimated timing under the 1.08V supply and the worst case corner shows that the test chip can achieve the maximum 952MS/S throughput. To our knowledge, the present Max-Log MAP decoder has the highest throughput with the modest hardware cost.",

author = "Tang, {Cheng Hao} and Wong, {Cheng Chi} and Chen, {Chih Lung} and Lin, {Chien Ching} and Hsie-Chia Chang",

year = "2006",

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doi = "10.1109/ASSCC.2006.357856",

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AU - Tang, Cheng Hao

AU - Wong, Cheng Chi

AU - Chen, Chih Lung

AU - Lin, Chien Ching

AU - Chang, Hsie-Chia

PY - 2006/12/1

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N2 - In this paper, a high-speed Max-Log MAP decoder is presented for soft-in and soft-out trellis decoding. The high throughput is achieved with a two-dimensional ACS design on the high-radix trellis structure, resulting in a highly parallel and area-efficient decoder. We further apply the retiming technique to reduce the critical path delay of ACS operation. After 0.13μm CMOS chip implementation, the decoder occupies 1.96mm2 area containing 220K gates. The estimated timing under the 1.08V supply and the worst case corner shows that the test chip can achieve the maximum 952MS/S throughput. To our knowledge, the present Max-Log MAP decoder has the highest throughput with the modest hardware cost.

AB - In this paper, a high-speed Max-Log MAP decoder is presented for soft-in and soft-out trellis decoding. The high throughput is achieved with a two-dimensional ACS design on the high-radix trellis structure, resulting in a highly parallel and area-efficient decoder. We further apply the retiming technique to reduce the critical path delay of ACS operation. After 0.13μm CMOS chip implementation, the decoder occupies 1.96mm2 area containing 220K gates. The estimated timing under the 1.08V supply and the worst case corner shows that the test chip can achieve the maximum 952MS/S throughput. To our knowledge, the present Max-Log MAP decoder has the highest throughput with the modest hardware cost.

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DO - 10.1109/ASSCC.2006.357856

M3 - Paper

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T2 - 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006

Y2 - 13 November 2006 through 15 November 2006

ER -

A 952MS/S max-log MAP decoder chip using radix-4 × 4 ACS architecture

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