A 94fps view synthesis engine for HD1080p video

Fu Jen Chang*, Yu Cheng Tseng, Tian-Sheuan Chang

*此作品的通信作者

研究成果: Conference contribution同行評審

7 引文 斯高帕斯(Scopus)

摘要

This paper presents a low-cost and high-throughput view synthesis engine based the view synthesis reference software (VSRS) algorithm. With the horizontal shift mode, we propose the row-based pipelined architecture to save the memory cost for original camera rotation issue. Owing to row-based method, internal Z-buffers for storing depth data can be reduced, and also the external bandwidth can be reduced. With the 90nm technology process, our view synthesis engine can achieve the throughput of 94.5 frame/sec for the HD1080p input with the gate count of 142.9k and the low memory cost of 54.72Kbytes.

原文English
主出版物標題2011 IEEE Visual Communications and Image Processing, VCIP 2011
DOIs
出版狀態Published - 1 十二月 2011
事件2011 IEEE Visual Communications and Image Processing, VCIP 2011 - Tainan, Taiwan
持續時間: 6 十一月 20119 十一月 2011

出版系列

名字2011 IEEE Visual Communications and Image Processing, VCIP 2011

Conference

Conference2011 IEEE Visual Communications and Image Processing, VCIP 2011
國家/地區Taiwan
城市Tainan
期間6/11/119/11/11

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