A 91-dB DR 20-kHz BW 5th-Order Multi-Step Incremental ADC for Sensor Interfaces by Re-Using a MASH 2-1 Modulator

Incremental ΔΣ analog-to-digital-converters (IADCs) possess indispensable advantages over conventional ΔΣ counterparts to interface the sensors. By adding global reset pulses to clear the memory in oversampled modulators and decimation filters, the reset pulses output the Nyquist-rate digitized samples. The hybrid of oversampling and Nyquist-rate conversions are thus easier to multiplex among multiple channels with very low conversion latency and much simpler decimation filters. These strengths favor the IADCs for high-resolution sensor data conversions, for example, column-parallel ADCs in image sensors and touch control panels. However, a first-order IADC (IADC1) is too slow and at least a second-order (IADC2) or a higher-order one is mandatory to shorten the conversion time and achieve good energy efficiency. To mitigate the instability of high-order IADCs and extend the non-overloaded input range, cascaded or multi-stage noise-shaping (MASH) modulators is an effective solution. In this paper, a MASH IADC (IADC2-1) incorporating an IADC2 and an IADC1 is proposed to operate in two steps by re-using and re-configuring the same circuits of IADC2-1. The third-order noise-shaping performance is boosted up to fifth-order with very low oversampling ratio (OSR) and very small area in 0.18 μm technology.