@inproceedings{840205fb412d4afc8e05d9a8ca5ae735,
title = "A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications",
abstract = "LDPC block codes (LDPC-BCs) have attracted great interests in recent years by highly parallel computation and good bit-error-rate performance, and one of the decoder implementation issues is high routing complexity. LDPC convolutional codes (LDPC-CCs) not only release routing complexity but also are natural to dynamic length of data frame. Thus, the codes are very suitable for video stream and pre-5G wireless communication systems. LDPC-CC decoder is composed of several concatenated processors, where the long FIFOs are usually the bottleneck of area and decoding latency. To improve hardware efficiency, we use overlapped architecture to share partial FIFO between processors. Furthermore, check node unit and hybrid-partitioned FIFO are proposed to increase throughput and pipeline efficiency. The measurement results of test chip in 65nm technology show that our work can achieves 7.72 Gb/s under 322MHz operating frequency. The decoder with 6 processors occupies an area of 1.19 mm2, drawing 410.5 mW of power with an energy efficiency of 8.75pJ/bit/proc.",
keywords = "digital signal, high throughput, LDPC, LDPC convolutional codes, overlapped architecture",
author = "Lin, {Chia Lung} and Liu, {Rong Jie} and Chih-Lung Chen and Hsie-Chia Chang and Chen-Yi Lee",
year = "2017",
month = feb,
day = "6",
doi = "10.1109/ASSCC.2016.7844204",
language = "English",
series = "2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "337--340",
booktitle = "2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings",
address = "United States",
note = "12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 ; Conference date: 07-11-2016 Through 09-11-2016",
}
