A 6Gbps serial link transmitter with pre-emphasis

Chang Min Chu; Chih Hua Chuang; Chi Hsien Lin; Shyh-Jye Jou

doi:10.1109/VDAT.2007.373213

A 6Gbps serial link transmitter with pre-emphasis

Chang Min Chu^*, Chih Hua Chuang, Chi Hsien Lin, Shyh-Jye Jou

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

5 引文斯高帕斯（Scopus）

摘要

In this paper, we propose a novel 6Gbps SATA transmitter, The transmitter is constructed by PISO, driver, pre-emphasis and PLL for a 1∼5 meter cable. A test chip of transmitter with PLL and on-chip termination is Implemented to verify the design methodology, The overall circuit is implemented in TSMC 0.18um 1P6M 1.8V CMOS process. The whole measured transmitter jitter is about 44ps and the power consumption is 68mW for 6Gbps case.

原文	English
主出版物標題	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOIs	https://doi.org/10.1109/VDAT.2007.373213
出版狀態	Published - 28 9月 2007
事件	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan 持續時間: 25 4月 2007 → 27 4月 2007

出版系列

名字	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Conference

Conference	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
國家/地區	Taiwan
城市	Hsinchu
期間	25/04/07 → 27/04/07

存取文件

10.1109/VDAT.2007.373213

其它文件與鏈接

Link to publication in Scopus

引用此

Chu, C. M., Chuang, C. H., Lin, C. H., & Jou, S-J. (2007). A 6Gbps serial link transmitter with pre-emphasis. 於 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers [4239405] (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2007.373213

@inproceedings{e1613c03c6b441be9de7108f09ffe0df,

title = "A 6Gbps serial link transmitter with pre-emphasis",

abstract = "In this paper, we propose a novel 6Gbps SATA transmitter, The transmitter is constructed by PISO, driver, pre-emphasis and PLL for a 1∼5 meter cable. A test chip of transmitter with PLL and on-chip termination is Implemented to verify the design methodology, The overall circuit is implemented in TSMC 0.18um 1P6M 1.8V CMOS process. The whole measured transmitter jitter is about 44ps and the power consumption is 68mW for 6Gbps case.",

author = "Chu, {Chang Min} and Chuang, {Chih Hua} and Lin, {Chi Hsien} and Shyh-Jye Jou",

year = "2007",

month = sep,

day = "28",

doi = "10.1109/VDAT.2007.373213",

language = "English",

isbn = "1424405831",

series = "2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers",

booktitle = "2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers",

note = "null ; Conference date: 25-04-2007 Through 27-04-2007",

}

Chu, CM, Chuang, CH, Lin, CH & Jou, S-J 2007, A 6Gbps serial link transmitter with pre-emphasis. 於 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers., 4239405, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007, Hsinchu, Taiwan, 25/04/07. https://doi.org/10.1109/VDAT.2007.373213

A 6Gbps serial link transmitter with pre-emphasis. / Chu, Chang Min; Chuang, Chih Hua; Lin, Chi Hsien 等.

2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 2007. 4239405 (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - A 6Gbps serial link transmitter with pre-emphasis

AU - Chu, Chang Min

AU - Chuang, Chih Hua

AU - Lin, Chi Hsien

AU - Jou, Shyh-Jye

PY - 2007/9/28

Y1 - 2007/9/28

N2 - In this paper, we propose a novel 6Gbps SATA transmitter, The transmitter is constructed by PISO, driver, pre-emphasis and PLL for a 1∼5 meter cable. A test chip of transmitter with PLL and on-chip termination is Implemented to verify the design methodology, The overall circuit is implemented in TSMC 0.18um 1P6M 1.8V CMOS process. The whole measured transmitter jitter is about 44ps and the power consumption is 68mW for 6Gbps case.

AB - In this paper, we propose a novel 6Gbps SATA transmitter, The transmitter is constructed by PISO, driver, pre-emphasis and PLL for a 1∼5 meter cable. A test chip of transmitter with PLL and on-chip termination is Implemented to verify the design methodology, The overall circuit is implemented in TSMC 0.18um 1P6M 1.8V CMOS process. The whole measured transmitter jitter is about 44ps and the power consumption is 68mW for 6Gbps case.

UR - http://www.scopus.com/inward/record.url?scp=34648824887&partnerID=8YFLogxK

U2 - 10.1109/VDAT.2007.373213

DO - 10.1109/VDAT.2007.373213

M3 - Conference contribution

AN - SCOPUS:34648824887

SN - 1424405831

SN - 9781424405831

T3 - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

BT - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Y2 - 25 April 2007 through 27 April 2007

ER -

A 6Gbps serial link transmitter with pre-emphasis

摘要

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Conference

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