A 65nm Node Strained SOI Technology with Slim Spacer

Fu Liang Yang; Chien Chao Huang; Hou Yu Chen; Jhon Jhy Liaw; Tang Xuan Chung; Hung Wei Chen; Chang Yun Chang; Cheng Chuan Huang; Kuang Hsin Chen; Di Hong Lee; Hsun Chih Tsao; Cheng Kuo Wen; Shui Ming Cheng; Yi Ming Sheu; Ke Wei Su; Chi Chun Chen; Tze Liang Lee; Shih Chang Chen; Chih Jian Chen; Cheng Hung Chang; Jhi Cheng Lu; Weng Chang; Chuan Ping Hou; Ying Ho Chen; Kuei Shun Chen; Ming Lu; Li Wei Kung; Yu Jun Chou; Fu Jye Liang; Jan Wen You; King Chang Shu; Bin Chang Chang; Jaw Jung Shin; Chun Kuang Chen; Tsai Sheng Gau; Bor Wen Chan; Yi Chun Huang; Han Jan Tao; Jyh Huei Chen; Yung Shun Chen; Yee Chia Yeo; Samuel K.H. Fung; Carlos H. Diaz; Chii Ming M. Wu; Burn J. Lin; Mong Song Liang; Jack Y.C. Sun; Chen-Ming Hu

doi:10.1109/IEDM.2003.1269359

A 65nm Node Strained SOI Technology with Slim Spacer

Fu Liang Yang^*
, Chien Chao Huang
, Hou Yu Chen
, Jhon Jhy Liaw
, Tang Xuan Chung
, Hung Wei Chen
, Chang Yun Chang
, Cheng Chuan Huang
, Kuang Hsin Chen
, Di Hong Lee
, Hsun Chih Tsao
, Cheng Kuo Wen
, Shui Ming Cheng
, Yi Ming Sheu
, Ke Wei Su
, Chi Chun Chen
, Tze Liang Lee
, Shih Chang Chen
, Chih Jian Chen
, Cheng Hung Chang

Jhi Cheng Lu, Weng Chang, Chuan Ping Hou, Ying Ho Chen, Kuei Shun Chen, Ming Lu, Li Wei Kung, Yu Jun Chou, Fu Jye Liang, Jan Wen You, King Chang Shu, Bin Chang Chang, Jaw Jung Shin, Chun Kuang Chen, Tsai Sheng Gau, Bor Wen Chan, Yi Chun Huang, Han Jan Tao, Jyh Huei Chen, Yung Shun Chen, Yee Chia Yeo, Samuel K.H. Fung, Carlos H. Diaz, Chii Ming M. Wu, Burn J. Lin, Mong Song Liang, Jack Y.C. Sun, Chen-Ming Hu

^*此作品的通信作者

國際半導體產業學院

研究成果: Conference article › 同行評審

14 引文斯高帕斯（Scopus）

摘要

A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 μA/μm for N-FET and P-FET, respectively, at an off-state leakage of 40 nA/μm using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce 10-20% layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15% higher inverter speed compared to planar SOI devices at the same drive current.

原文	English
頁（從 - 到）	627-630
頁數	4
期刊	Technical Digest - International Electron Devices Meeting
DOIs	https://doi.org/10.1109/IEDM.2003.1269359
出版狀態	Published - 2003
事件	IEEE International Electron Devices Meeting - Washington, DC, 美國持續時間: 8 12月 2003 → 10 12月 2003

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10.1109/IEDM.2003.1269359

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Link to publication in Scopus

引用此

Yang, F. L., Huang, C. C., Chen, H. Y., Liaw, J. J., Chung, T. X., Chen, H. W., Chang, C. Y., Huang, C. C., Chen, K. H., Lee, D. H., Tsao, H. C., Wen, C. K., Cheng, S. M., Sheu, Y. M., Su, K. W., Chen, C. C., Lee, T. L., Chen, S. C., Chen, C. J., ... Hu, C.-M. (2003). A 65nm Node Strained SOI Technology with Slim Spacer. Technical Digest - International Electron Devices Meeting, 627-630. https://doi.org/10.1109/IEDM.2003.1269359

@article{e1d79a4c516945feb0a9da373b03acef,

title = "A 65nm Node Strained SOI Technology with Slim Spacer",

abstract = "A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 μA/μm for N-FET and P-FET, respectively, at an off-state leakage of 40 nA/μm using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce 10-20\% layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15\% higher inverter speed compared to planar SOI devices at the same drive current.",

author = "Yang, \{Fu Liang\} and Huang, \{Chien Chao\} and Chen, \{Hou Yu\} and Liaw, \{Jhon Jhy\} and Chung, \{Tang Xuan\} and Chen, \{Hung Wei\} and Chang, \{Chang Yun\} and Huang, \{Cheng Chuan\} and Chen, \{Kuang Hsin\} and Lee, \{Di Hong\} and Tsao, \{Hsun Chih\} and Wen, \{Cheng Kuo\} and Cheng, \{Shui Ming\} and Sheu, \{Yi Ming\} and Su, \{Ke Wei\} and Chen, \{Chi Chun\} and Lee, \{Tze Liang\} and Chen, \{Shih Chang\} and Chen, \{Chih Jian\} and Chang, \{Cheng Hung\} and Lu, \{Jhi Cheng\} and Weng Chang and Hou, \{Chuan Ping\} and Chen, \{Ying Ho\} and Chen, \{Kuei Shun\} and Ming Lu and Kung, \{Li Wei\} and Chou, \{Yu Jun\} and Liang, \{Fu Jye\} and You, \{Jan Wen\} and Shu, \{King Chang\} and Chang, \{Bin Chang\} and Shin, \{Jaw Jung\} and Chen, \{Chun Kuang\} and Gau, \{Tsai Sheng\} and Chan, \{Bor Wen\} and Huang, \{Yi Chun\} and Tao, \{Han Jan\} and Chen, \{Jyh Huei\} and Chen, \{Yung Shun\} and Yeo, \{Yee Chia\} and Fung, \{Samuel K.H.\} and Diaz, \{Carlos H.\} and Wu, \{Chii Ming M.\} and Lin, \{Burn J.\} and Liang, \{Mong Song\} and Sun, \{Jack Y.C.\} and Chen-Ming Hu",

year = "2003",

doi = "10.1109/IEDM.2003.1269359",

language = "English",

pages = "627--630",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Electron Devices Meeting ; Conference date: 08-12-2003 Through 10-12-2003",

}

Yang, FL, Huang, CC, Chen, HY, Liaw, JJ, Chung, TX, Chen, HW, Chang, CY, Huang, CC, Chen, KH, Lee, DH, Tsao, HC, Wen, CK, Cheng, SM, Sheu, YM, Su, KW, Chen, CC, Lee, TL, Chen, SC, Chen, CJ, Chang, CH, Lu, JC, Chang, W, Hou, CP, Chen, YH, Chen, KS, Lu, M, Kung, LW, Chou, YJ, Liang, FJ, You, JW, Shu, KC, Chang, BC, Shin, JJ, Chen, CK, Gau, TS, Chan, BW, Huang, YC, Tao, HJ, Chen, JH, Chen, YS, Yeo, YC, Fung, SKH, Diaz, CH, Wu, CMM, Lin, BJ, Liang, MS, Sun, JYC & Hu, C-M 2003, 'A 65nm Node Strained SOI Technology with Slim Spacer', Technical Digest - International Electron Devices Meeting, 頁 627-630. https://doi.org/10.1109/IEDM.2003.1269359

TY - JOUR

T1 - A 65nm Node Strained SOI Technology with Slim Spacer

AU - Yang, Fu Liang

AU - Huang, Chien Chao

AU - Chen, Hou Yu

AU - Liaw, Jhon Jhy

AU - Chung, Tang Xuan

AU - Chen, Hung Wei

AU - Chang, Chang Yun

AU - Huang, Cheng Chuan

AU - Chen, Kuang Hsin

AU - Lee, Di Hong

AU - Tsao, Hsun Chih

AU - Wen, Cheng Kuo

AU - Cheng, Shui Ming

AU - Sheu, Yi Ming

AU - Su, Ke Wei

AU - Chen, Chi Chun

AU - Lee, Tze Liang

AU - Chen, Shih Chang

AU - Chen, Chih Jian

AU - Chang, Cheng Hung

AU - Lu, Jhi Cheng

AU - Chang, Weng

AU - Hou, Chuan Ping

AU - Chen, Ying Ho

AU - Chen, Kuei Shun

AU - Lu, Ming

AU - Kung, Li Wei

AU - Chou, Yu Jun

AU - Liang, Fu Jye

AU - You, Jan Wen

AU - Shu, King Chang

AU - Chang, Bin Chang

AU - Shin, Jaw Jung

AU - Chen, Chun Kuang

AU - Gau, Tsai Sheng

AU - Chan, Bor Wen

AU - Huang, Yi Chun

AU - Tao, Han Jan

AU - Chen, Jyh Huei

AU - Chen, Yung Shun

AU - Yeo, Yee Chia

AU - Fung, Samuel K.H.

AU - Diaz, Carlos H.

AU - Wu, Chii Ming M.

AU - Lin, Burn J.

AU - Liang, Mong Song

AU - Sun, Jack Y.C.

AU - Hu, Chen-Ming

PY - 2003

Y1 - 2003

N2 - A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 μA/μm for N-FET and P-FET, respectively, at an off-state leakage of 40 nA/μm using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce 10-20% layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15% higher inverter speed compared to planar SOI devices at the same drive current.

AB - A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 μA/μm for N-FET and P-FET, respectively, at an off-state leakage of 40 nA/μm using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce 10-20% layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15% higher inverter speed compared to planar SOI devices at the same drive current.

UR - https://www.scopus.com/pages/publications/17644444298

U2 - 10.1109/IEDM.2003.1269359

DO - 10.1109/IEDM.2003.1269359

M3 - Conference article

AN - SCOPUS:17644444298

SN - 0163-1918

SP - 627

EP - 630

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - IEEE International Electron Devices Meeting

Y2 - 8 December 2003 through 10 December 2003

ER -

A 65nm Node Strained SOI Technology with Slim Spacer

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