TY - GEN
T1 - A 650 pW,-71 dB PSRR, 205°C Temperature Range Hybrid Voltage Reference with Curvature-Based Temperature Compensation and SBFL Techniques
AU - Shao, Cheng Ze
AU - Liao, Yu-Te
N1 - Publisher Copyright:
© 2021 JSAP.
PY - 2021/6/13
Y1 - 2021/6/13
N2 - This paper presents a 650 pW 1V hybrid voltage reference with curvature-based temperature compensation in a 0.18-μm CMOS process. The design achieves a 45 ppm/°C from-55 to 150 °C, line sensitivity of 0.016 %/V and PSRR of-71 dB at 100 Hz by employing a self-biasing feedback loop.
AB - This paper presents a 650 pW 1V hybrid voltage reference with curvature-based temperature compensation in a 0.18-μm CMOS process. The design achieves a 45 ppm/°C from-55 to 150 °C, line sensitivity of 0.016 %/V and PSRR of-71 dB at 100 Hz by employing a self-biasing feedback loop.
UR - http://www.scopus.com/inward/record.url?scp=85111881922&partnerID=8YFLogxK
U2 - 10.23919/VLSICircuits52068.2021.9492407
DO - 10.23919/VLSICircuits52068.2021.9492407
M3 - Conference contribution
AN - SCOPUS:85111881922
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
BT - 2021 Symposium on VLSI Circuits, VLSI Circuits 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th Symposium on VLSI Circuits, VLSI Circuits 2021
Y2 - 13 June 2021 through 19 June 2021
ER -