A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications

Shiang Yu Hung; Shao Wei Yen; Chih Lung Chen; Hsie-Chia Chang; Shyh-Jye Jou; Chen-Yi Lee

doi:10.1109/ASSCC.2010.5716617

A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications

Shiang Yu Hung^*, Shao Wei Yen, Chih Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee

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研究成果: Conference contribution › 同行評審

11 引文斯高帕斯（Scopus）

摘要

A LDPC decoder chip supporting four code rates of IEEE 802.15.3c applications is presented. The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration number while maintaining similar performance. In addition, the reconfigurable 8/16/32-input sorter is designed to deal with four LDPC codes. In order to alleviate routing complexity, both of the reallocation of sorter inputs and pre-coding routing network are proposed to reduce the input numbers of multiplexers by 64%. Fabricated in 65-nm 1P10M CMOS process, this test chip can achieve maximum 5.79Gbps throughput for the highest code rate code while the hardware efficiency and energy efficiency are 3.7Gbps/mm² and 62.4pJ/bit, respectively.

原文	English
主出版物標題	2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
頁面	309-312
頁數	4
DOIs	https://doi.org/10.1109/ASSCC.2010.5716617
出版狀態	Published - 1 12月 2010
事件	2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing, China 持續時間: 8 11月 2010 → 10 11月 2010

出版系列

名字	2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Conference

Conference	2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
國家/地區	China
城市	Beijing
期間	8/11/10 → 10/11/10

UN SDG

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10.1109/ASSCC.2010.5716617

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@inproceedings{5631dd5553404733b088263e9df530a5,

title = "A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications",

abstract = "A LDPC decoder chip supporting four code rates of IEEE 802.15.3c applications is presented. The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration number while maintaining similar performance. In addition, the reconfigurable 8/16/32-input sorter is designed to deal with four LDPC codes. In order to alleviate routing complexity, both of the reallocation of sorter inputs and pre-coding routing network are proposed to reduce the input numbers of multiplexers by 64%. Fabricated in 65-nm 1P10M CMOS process, this test chip can achieve maximum 5.79Gbps throughput for the highest code rate code while the hardware efficiency and energy efficiency are 3.7Gbps/mm2 and 62.4pJ/bit, respectively.",

author = "Hung, {Shiang Yu} and Yen, {Shao Wei} and Chen, {Chih Lung} and Hsie-Chia Chang and Shyh-Jye Jou and Chen-Yi Lee",

year = "2010",

month = dec,

day = "1",

doi = "10.1109/ASSCC.2010.5716617",

language = "English",

isbn = "9781424482979",

series = "2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010",

pages = "309--312",

booktitle = "2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010",

note = "null ; Conference date: 08-11-2010 Through 10-11-2010",

}

Hung, SY, Yen, SW, Chen, CL, Chang, H-C , Jou, S-J & Lee, C-Y 2010, A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications. 於 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010., 5716617, 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, 頁 309-312, 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, Beijing, China, 8/11/10. https://doi.org/10.1109/ASSCC.2010.5716617

TY - GEN

T1 - A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications

AU - Hung, Shiang Yu

AU - Yen, Shao Wei

AU - Chen, Chih Lung

AU - Chang, Hsie-Chia

AU - Jou, Shyh-Jye

AU - Lee, Chen-Yi

PY - 2010/12/1

Y1 - 2010/12/1

N2 - A LDPC decoder chip supporting four code rates of IEEE 802.15.3c applications is presented. The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration number while maintaining similar performance. In addition, the reconfigurable 8/16/32-input sorter is designed to deal with four LDPC codes. In order to alleviate routing complexity, both of the reallocation of sorter inputs and pre-coding routing network are proposed to reduce the input numbers of multiplexers by 64%. Fabricated in 65-nm 1P10M CMOS process, this test chip can achieve maximum 5.79Gbps throughput for the highest code rate code while the hardware efficiency and energy efficiency are 3.7Gbps/mm2 and 62.4pJ/bit, respectively.

AB - A LDPC decoder chip supporting four code rates of IEEE 802.15.3c applications is presented. The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration number while maintaining similar performance. In addition, the reconfigurable 8/16/32-input sorter is designed to deal with four LDPC codes. In order to alleviate routing complexity, both of the reallocation of sorter inputs and pre-coding routing network are proposed to reduce the input numbers of multiplexers by 64%. Fabricated in 65-nm 1P10M CMOS process, this test chip can achieve maximum 5.79Gbps throughput for the highest code rate code while the hardware efficiency and energy efficiency are 3.7Gbps/mm2 and 62.4pJ/bit, respectively.

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Y2 - 8 November 2010 through 10 November 2010

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A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications

摘要

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