A 521-bit dual-field elliptic curve cryptographic processor with power analysis resistance

Jen Wei Lee*, Yao Lin Chen, Chih Yeh Tseng, Hsie-Chia Chang, Chen-Yi Lee

*此作品的通信作者

    研究成果: Conference contribution同行評審

    28 引文 斯高帕斯(Scopus)

    摘要

    Recently, several hardware implementations for elliptic curve cryptography have been proposed but few of them considered the dual-field functions, real-time requirement, hardware efficiency, and power analysis resistance as a whole. In this paper, a new unified division algorithm and a free pre-computation scheme are introduced to accelerate the GF(p)/GF(2n) elliptic curve arithmetic functions. The overall hardware is optimized by a very compact Galois field arithmetic unit with the fully pipelined technique. Moreover, a key-blinded technique with regular calculation is designed against the power analysis attacks without degrading clock speed. After fabricated in 90nm CMOS 1P9M process, our ECC processor occupied 0.55mm2 can perform the scalar multiplication in 19.2ms over GF(p521) and 8.2ms over GF(2409), respectively.

    原文English
    主出版物標題ESSCIRC 2010 - 36th European Solid State Circuits Conference
    頁面206-209
    頁數4
    DOIs
    出版狀態Published - 27 12月 2010
    事件36th European Solid State Circuits Conference, ESSCIRC 2010 - Sevilla, Spain
    持續時間: 14 9月 201016 9月 2010

    出版系列

    名字ESSCIRC 2010 - 36th European Solid State Circuits Conference

    Conference

    Conference36th European Solid State Circuits Conference, ESSCIRC 2010
    國家/地區Spain
    城市Sevilla
    期間14/09/1016/09/10

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