A memory-based (ms = 50, dv = 2, dc = 4) nonbinary LDPC convolutional code (NB-LDPC-CC) decoder over GF(256) with layered scheduling is presented. The proposed architecture-aware construction features fewer memory banks, low degree, low period, and better performance. To the best of our knowledge, this is the first architecture discussion and implementation for NB-LDPC-CC decoders. We optimized the architecture of message first-in-first-out (M-FIFO), check node unit, and variable node unit in terms of area and throughput. Jointly designing code and architecture, overall normalized area efficiency can be enhanced by more then six times with respect to decoders of nonbinary LDPC block codes (NB-LDPC BCs). After fabricated in 90nm CMOS, our prototype NB-LDPC-CC decoder chip can achieve maximum throughput of 22.8Mbps with frequency of 285MHz. The measured average power is 211mW at a typical operating voltage of 1.0V.
|出版狀態||Published - 1 12月 2012|
|事件||2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan|
持續時間: 12 11月 2012 → 14 11月 2012
|Conference||2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012|
|期間||12/11/12 → 14/11/12|