This paper presents the design of a fully integrated, 50 Gb/s PAM-4 transmitter, which consists of an on-chip pseudorandom word generator (PRWG), a 16:2 quarter-rate serializer with 4-tap FFE, and on-chip duty-cycle calibration (DCC) and quadrature phase error calibration (QEC) loops. The dual-loop DCC and QEC can be operated concurrently on-the-fly to suppress the deterministic data jitter. Incorporating the proposed technique, the eye opening is improved by 30%. To facilitate built-in-self-test (BIST) under high speed operation, the PRWG provides 16-path parallel test patterns, which correspond to PRBS-13Q after serializer. The output buffer employs inductive shunt-series peaking for broad band impedance matching and bandwidth enhancement. The bandwidth is extended more than twice while the return loss is reduced by more 4dB. The experimental prototype is fabricated in a TSMC 28 nm CMOS process, and the core area is 0.214 mm2. The whole transmitter consumes 143.4 mW at 50 Gb/s operation.
|頁（從 - 到）||2820 - 2824|
|期刊||IEEE Transactions on Circuits and Systems I: Regular Papers|
|出版狀態||Published - 8月 2021|