TY - GEN
T1 - A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration
AU - Lin, Yu Ting
AU - Chen, Wei Zen
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/11/9
Y1 - 2020/11/9
N2 - This paper presents the design of a fully integrated, 50 Gb/s PAM-4 transmitter, which consists of an on-chip pseudorandom word generator (PRWG), a 16:1 quarter-rate serializer with 4-tap FFE, and on-chip duty-cycle (DCC) and quadrature phase error calibration (QEC) loops. The dual-loop DCC and QEC can be operated concurrently on-the-fly to suppress the deterministic data jitter. Incorporating the proposed technique, the eye opening is improved by 30 %. To facilitate built-in-self-test (BIST) under high speed operation, the PRWG provides 16-path parallel test patterns, which correspond to PRBS-13Q after serializer. The experimental prototype is fabricated in a TSMC 28 nm CMOS process, and the core area is 0.214 mm2. The whole transmitter consumes 143.4 mW at 50 Gb/s operation
AB - This paper presents the design of a fully integrated, 50 Gb/s PAM-4 transmitter, which consists of an on-chip pseudorandom word generator (PRWG), a 16:1 quarter-rate serializer with 4-tap FFE, and on-chip duty-cycle (DCC) and quadrature phase error calibration (QEC) loops. The dual-loop DCC and QEC can be operated concurrently on-the-fly to suppress the deterministic data jitter. Incorporating the proposed technique, the eye opening is improved by 30 %. To facilitate built-in-self-test (BIST) under high speed operation, the PRWG provides 16-path parallel test patterns, which correspond to PRBS-13Q after serializer. The experimental prototype is fabricated in a TSMC 28 nm CMOS process, and the core area is 0.214 mm2. The whole transmitter consumes 143.4 mW at 50 Gb/s operation
KW - Duty-cycle calibration (DCC)
KW - Feedforward equalizer (FFE)
KW - Pseudorandom word generator (PRWG)
KW - Quadrature clock generator (QCG)
KW - Quadrature phase error calibration(QEC)
UR - http://www.scopus.com/inward/record.url?scp=85100948742&partnerID=8YFLogxK
U2 - 10.1109/A-SSCC48613.2020.9336134
DO - 10.1109/A-SSCC48613.2020.9336134
M3 - Conference contribution
AN - SCOPUS:85100948742
T3 - 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020
BT - 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 16th IEEE Asian Solid-State Circuits Conference, A-SSCC 2020
Y2 - 9 November 2020 through 11 November 2020
ER -