A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration

Yu Ting Lin, Wei Zen Chen*

*此作品的通信作者

    研究成果: Conference contribution同行評審

    摘要

    This paper presents the design of a fully integrated, 50 Gb/s PAM-4 transmitter, which consists of an on-chip pseudorandom word generator (PRWG), a 16:1 quarter-rate serializer with 4-tap FFE, and on-chip duty-cycle (DCC) and quadrature phase error calibration (QEC) loops. The dual-loop DCC and QEC can be operated concurrently on-the-fly to suppress the deterministic data jitter. Incorporating the proposed technique, the eye opening is improved by 30 %. To facilitate built-in-self-test (BIST) under high speed operation, the PRWG provides 16-path parallel test patterns, which correspond to PRBS-13Q after serializer. The experimental prototype is fabricated in a TSMC 28 nm CMOS process, and the core area is 0.214 mm2. The whole transmitter consumes 143.4 mW at 50 Gb/s operation

    原文English
    主出版物標題2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020
    發行者Institute of Electrical and Electronics Engineers Inc.
    ISBN(電子)9781728184364
    DOIs
    出版狀態Published - 9 十一月 2020
    事件16th IEEE Asian Solid-State Circuits Conference, A-SSCC 2020 - Virtual, Hiroshima, Japan
    持續時間: 9 十一月 202011 十一月 2020

    出版系列

    名字2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020

    Conference

    Conference16th IEEE Asian Solid-State Circuits Conference, A-SSCC 2020
    國家/地區Japan
    城市Virtual, Hiroshima
    期間9/11/2011/11/20

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