A 5-GHz CMOS Double-Quadrature Receiver for IEEE 802.11a Applications

Chung-Yu Wu; Chung Yun Chou

doi:10.1109/VLSIC.2003.1221186

A 5-GHz CMOS Double-Quadrature Receiver for IEEE 802.11a Applications

Chung-Yu Wu^*
, Chung Yun Chou

^*此作品的通信作者

研究成果: Paper › 同行評審

5 引文斯高帕斯（Scopus）

摘要

A 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0. 18μm CMOS technology, the receiver chip can achieve 50.6dB image-rejection with the power dissipation of 22.4mW at 1.8-V voltage supply.

原文	English
頁面	149-152
頁數	4
DOIs	https://doi.org/10.1109/VLSIC.2003.1221186
出版狀態	Published - 2003
事件	2003 Symposium on VLSI Circuits - Kyoto, 日本持續時間: 12 6月 2003 → 14 6月 2003

Conference

Conference	2003 Symposium on VLSI Circuits
國家/地區	日本
城市	Kyoto
期間	12/06/03 → 14/06/03

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10.1109/VLSIC.2003.1221186

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Link to publication in Scopus

引用此

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title = "A 5-GHz CMOS Double-Quadrature Receiver for IEEE 802.11a Applications",

abstract = "A 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0. 18μm CMOS technology, the receiver chip can achieve 50.6dB image-rejection with the power dissipation of 22.4mW at 1.8-V voltage supply.",

author = "Chung-Yu Wu and Chou, \{Chung Yun\}",

year = "2003",

doi = "10.1109/VLSIC.2003.1221186",

language = "English",

pages = "149--152",

note = "2003 Symposium on VLSI Circuits ; Conference date: 12-06-2003 Through 14-06-2003",

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AU - Wu, Chung-Yu

AU - Chou, Chung Yun

PY - 2003

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N2 - A 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0. 18μm CMOS technology, the receiver chip can achieve 50.6dB image-rejection with the power dissipation of 22.4mW at 1.8-V voltage supply.

AB - A 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0. 18μm CMOS technology, the receiver chip can achieve 50.6dB image-rejection with the power dissipation of 22.4mW at 1.8-V voltage supply.

UR - https://www.scopus.com/pages/publications/0141426747

U2 - 10.1109/VLSIC.2003.1221186

DO - 10.1109/VLSIC.2003.1221186

M3 - Paper

AN - SCOPUS:0141426747

SP - 149

EP - 152

T2 - 2003 Symposium on VLSI Circuits

Y2 - 12 June 2003 through 14 June 2003

ER -

A 5-GHz CMOS Double-Quadrature Receiver for IEEE 802.11a Applications

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