A 5-GHz CMOS Double-Quadrature Receiver for IEEE 802.11a Applications

Chung-Yu Wu*, Chung Yun Chou

*此作品的通信作者

    研究成果: Paper同行評審

    5 引文 斯高帕斯(Scopus)

    摘要

    A 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0. 18μm CMOS technology, the receiver chip can achieve 50.6dB image-rejection with the power dissipation of 22.4mW at 1.8-V voltage supply.

    原文English
    頁面149-152
    頁數4
    DOIs
    出版狀態Published - 2003
    事件2003 Symposium on VLSI Circuits - Kyoto, 日本
    持續時間: 12 6月 200314 6月 2003

    Conference

    Conference2003 Symposium on VLSI Circuits
    國家/地區日本
    城市Kyoto
    期間12/06/0314/06/03

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