摘要
A 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0. 18μm CMOS technology, the receiver chip can achieve 50.6dB image-rejection with the power dissipation of 22.4mW at 1.8-V voltage supply.
原文 | English |
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頁面 | 149-152 |
頁數 | 4 |
DOIs | |
出版狀態 | Published - 2003 |
事件 | 2003 Symposium on VLSI Circuits - Kyoto, 日本 持續時間: 12 6月 2003 → 14 6月 2003 |
Conference
Conference | 2003 Symposium on VLSI Circuits |
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國家/地區 | 日本 |
城市 | Kyoto |
期間 | 12/06/03 → 14/06/03 |