A 4.2 nW and 18 ppm/°C temperature coefficient leakage-based square root compensation (LSRC) CMOS voltage reference

Chao Jen Huang, Yan Jiun Lai, Yu Jheng Ou Yang, Hung Wei Chen, Chun Chieh Kuo, Ke-Horng Chen*, Ying Hsi Lin, Shian Ru Lin, Tsung Yen Tsai

*此作品的通信作者

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

State-of-the-art CMOS-based voltage reference suffer from a trade-off between power dissipation and temperature coefficient (TC) due to the limited order of compensation in an advanced process which features a low supplied voltage (11.2 V). The proposed voltage reference with leakage-based square root compensation (LSRC) technique bias the substrate to offset TC with ultra-low leakage current (100300 pA). On the other hand, the architecture provides an extensible order of compensation which is independent of voltage headroom. The two LSRC branches voltage reference implemented in 40 nm CMOS process achieves a within-wafer σ/μ of 0.204 and a TC of 18 ppm/°C with a power consumption of 4.2 nW.

原文English
文章編號8676347
頁(從 - 到)728-732
頁數5
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
66
發行號5
DOIs
出版狀態Published - 1 五月 2019

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