A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

Chi Shin Chang, Hao I. Yang, Wei Nan Liao, Yi Wei Lin, Nan Chun Lien, Chien Hen Chen, Ching Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming Hsien Tu, Huan Shun Huang, Yong Jyun Hu, Paul Sen Kan, Cheng Yo Cheng, Wei Chang Wang, Jian Hao Wang, Kuen Di Lee, Chia Cheng Chen, Wei Chiang Shih

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 800MHz@1.2V and 25°C. The measured power consumption is 23.21mW (Active)/2.42mW (Leakage) at 1.2V, TT, 25°C; and 6.01mW (Active)/0.35mW (Leakage) at 0.7V, TT, 25°C.

原文English
主出版物標題2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
頁面1468-1471
頁數4
DOIs
出版狀態Published - 9 9月 2013
事件2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China
持續時間: 19 5月 201323 5月 2013

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Conference

Conference2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
國家/地區China
城市Beijing
期間19/05/1323/05/13

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