A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

Chi Shin Chang; Hao I. Yang; Wei Nan Liao; Yi Wei Lin; Nan Chun Lien; Chien Hen Chen; Ching Te Chuang; Wei Hwang; Shyh-Jye Jou; Ming Hsien Tu; Huan Shun Huang; Yong Jyun Hu; Paul Sen Kan; Cheng Yo Cheng; Wei Chang Wang; Jian Hao Wang; Kuen Di Lee; Chia Cheng Chen; Wei Chiang Shih

doi:10.1109/ISCAS.2013.6572134

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

Chi Shin Chang, Hao I. Yang, Wei Nan Liao, Yi Wei Lin, Nan Chun Lien, Chien Hen Chen, Ching Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming Hsien Tu, Huan Shun Huang, Yong Jyun Hu, Paul Sen Kan, Cheng Yo Cheng, Wei Chang Wang, Jian Hao Wang, Kuen Di Lee, Chia Cheng Chen, Wei Chiang Shih

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研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 800MHz@1.2V and 25°C. The measured power consumption is 23.21mW (Active)/2.42mW (Leakage) at 1.2V, TT, 25°C; and 6.01mW (Active)/0.35mW (Leakage) at 0.7V, TT, 25°C.

原文	English
主出版物標題	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
頁面	1468-1471
頁數	4
DOIs	https://doi.org/10.1109/ISCAS.2013.6572134
出版狀態	Published - 9 9月 2013
事件	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China 持續時間: 19 5月 2013 → 23 5月 2013

出版系列

名字	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN（列印）	0271-4310

Conference

Conference	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
國家/地區	China
城市	Beijing
期間	19/05/13 → 23/05/13

存取文件

10.1109/ISCAS.2013.6572134

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Link to publication in Scopus

引用此

Chang, C. S., Yang, H. I., Liao, W. N., Lin, Y. W., Lien, N. C., Chen, C. H., Chuang, C. T., Hwang, W., Jou, S-J., Tu, M. H., Huang, H. S., Hu, Y. J., Kan, P. S., Cheng, C. Y., Wang, W. C., Wang, J. H., Lee, K. D., Chen, C. C., & Shih, W. C. (2013). A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. 於 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 (頁 1468-1471). [6572134] (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2013.6572134

@inproceedings{d6834a2d6cbb42578e531ff364d1538b,

title = "A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist",

abstract = "We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 800MHz@1.2V and 25°C. The measured power consumption is 23.21mW (Active)/2.42mW (Leakage) at 1.2V, TT, 25°C; and 6.01mW (Active)/0.35mW (Leakage) at 0.7V, TT, 25°C.",

author = "Chang, {Chi Shin} and Yang, {Hao I.} and Liao, {Wei Nan} and Lin, {Yi Wei} and Lien, {Nan Chun} and Chen, {Chien Hen} and Chuang, {Ching Te} and Wei Hwang and Shyh-Jye Jou and Tu, {Ming Hsien} and Huang, {Huan Shun} and Hu, {Yong Jyun} and Kan, {Paul Sen} and Cheng, {Cheng Yo} and Wang, {Wei Chang} and Wang, {Jian Hao} and Lee, {Kuen Di} and Chen, {Chia Cheng} and Shih, {Wei Chiang}",

year = "2013",

month = sep,

day = "9",

doi = "10.1109/ISCAS.2013.6572134",

language = "English",

isbn = "9781467357609",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "1468--1471",

booktitle = "2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013",

note = "null ; Conference date: 19-05-2013 Through 23-05-2013",

}

Chang, CS, Yang, HI, Liao, WN, Lin, YW, Lien, NC, Chen, CH, Chuang, CT, Hwang, W, Jou, S-J, Tu, MH, Huang, HS, Hu, YJ, Kan, PS, Cheng, CY, Wang, WC, Wang, JH, Lee, KD, Chen, CC & Shih, WC 2013, A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. 於 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013., 6572134, Proceedings - IEEE International Symposium on Circuits and Systems, 頁 1468-1471, 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013, Beijing, China, 19/05/13. https://doi.org/10.1109/ISCAS.2013.6572134

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. / Chang, Chi Shin; Yang, Hao I.; Liao, Wei Nan 等.

2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013. 2013. p. 1468-1471 6572134 (Proceedings - IEEE International Symposium on Circuits and Systems).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

AU - Chang, Chi Shin

AU - Yang, Hao I.

AU - Liao, Wei Nan

AU - Lin, Yi Wei

AU - Lien, Nan Chun

AU - Chen, Chien Hen

AU - Chuang, Ching Te

AU - Hwang, Wei

AU - Jou, Shyh-Jye

AU - Tu, Ming Hsien

AU - Huang, Huan Shun

AU - Hu, Yong Jyun

AU - Kan, Paul Sen

AU - Cheng, Cheng Yo

AU - Wang, Wei Chang

AU - Wang, Jian Hao

AU - Lee, Kuen Di

AU - Chen, Chia Cheng

AU - Shih, Wei Chiang

PY - 2013/9/9

Y1 - 2013/9/9

N2 - We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 800MHz@1.2V and 25°C. The measured power consumption is 23.21mW (Active)/2.42mW (Leakage) at 1.2V, TT, 25°C; and 6.01mW (Active)/0.35mW (Leakage) at 0.7V, TT, 25°C.

AB - We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 800MHz@1.2V and 25°C. The measured power consumption is 23.21mW (Active)/2.42mW (Leakage) at 1.2V, TT, 25°C; and 6.01mW (Active)/0.35mW (Leakage) at 0.7V, TT, 25°C.

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U2 - 10.1109/ISCAS.2013.6572134

DO - 10.1109/ISCAS.2013.6572134

M3 - Conference contribution

AN - SCOPUS:84883365125

SN - 9781467357609

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 1468

EP - 1471

BT - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013

Y2 - 19 May 2013 through 23 May 2013

ER -

Chang CS, Yang HI, Liao WN, Lin YW, Lien NC, Chen CH 等. A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. 於 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013. 2013. p. 1468-1471. 6572134. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2013.6572134

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

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