A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control

Wei Nan Liao, Nan Chun Lien, Chi Shin Chang, Li Wei Chu, Hao I. Yang, Ching Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming Hsien Tu, Huan Shun Huang, Jian Hao Wang, Paul Sen Kan, Yong Jyun Hu

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

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Engineering & Materials Science