A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control

Wei Nan Liao, Nan Chun Lien, Chi Shin Chang, Li Wei Chu, Hao I. Yang, Ching Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming Hsien Tu, Huan Shun Huang, Jian Hao Wang, Paul Sen Kan, Yong Jyun Hu

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

This paper presents a 40nm 1.0Mb pipeline 6T SRAM featuring digital-based Bit-Line Under-Drive (BLUD) with large-signal sensing and Three-Step-Up Word-Line (TSUWL) to improve RSNM, Read performance and Write-ability. An Adaptive Data-Aware Write-Assist (ADAWA) with VCS tracking is employed to further improve Write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An Adaptive Voltage Detector (AVD) with binary boosting control is used to mitigate gate dielectric over-stress. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 1.07GHz@1.2V and 887MHz@1.1V at 25°C. The measured power consumption is 43.47mW (Active)/3.91mW (Leakage) at 1.1V and 8.97mW (Active)/0.52mW (Leakage) at 0.7V, TT, 25°C.

原文English
主出版物標題Proceedings - IEEE 26th International SOC Conference, SOCC 2013
發行者IEEE Computer Society
頁面110-115
頁數6
ISBN(列印)9781479911660
DOIs
出版狀態Published - 1 1月 2013
事件26th IEEE International System-on-Chip Conference, SOCC 2013 - Erlangen, Germany
持續時間: 4 9月 20136 9月 2013

出版系列

名字International System on Chip Conference
ISSN(列印)2164-1676
ISSN(電子)2164-1706

Conference

Conference26th IEEE International System-on-Chip Conference, SOCC 2013
國家/地區Germany
城市Erlangen
期間4/09/136/09/13

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