A 40 nm 535 Mbps multiple code-rate turbo decoder chip using reciprocal dual trellis

Chen Yang Lin; Cheng Chi Wong; Hsie-Chia Chang

doi:10.1109/IPEC.2012.6522659

A 40 nm 535 Mbps multiple code-rate turbo decoder chip using reciprocal dual trellis

Chen Yang Lin, Cheng Chi Wong, Hsie-Chia Chang

研究成果: Paper › 同行評審

1 引文斯高帕斯（Scopus）

摘要

This paper presents a turbo decoder chip which can decode code rate k/(k + 1) constituent convolutional codes for k=1, 2, 4, 8, and 16. After replacing the constituent code by its code rate 1/(k + 1) reciprocal dual code, we can derive a smaller codeword space and design a simpler decoding trellis structure for high code-rate SISO decoder. In addition, two parallel SISO decoders are exploited in our turbo decoder by using the quadratic permutation polynomial (QPP) interleaver to improve the decoding speed. After fabricated in 1P9M CMOS 40 nm process, the proposed decoder with 1.27 mm² core area can achieve 535 Mbps throughput at 8/9 code rate, and the energy efficiency is 0.068 nJ/bit/iteration at 0.9 V.

原文	English
頁面	197-200
頁數	4
DOIs	https://doi.org/10.1109/IPEC.2012.6522659
出版狀態	Published - 1 12月 2012
事件	2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan 持續時間: 12 11月 2012 → 14 11月 2012

Conference

Conference	2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
國家/地區	Japan
城市	Kobe
期間	12/11/12 → 14/11/12

UN SDG

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10.1109/IPEC.2012.6522659

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title = "A 40 nm 535 Mbps multiple code-rate turbo decoder chip using reciprocal dual trellis",

abstract = "This paper presents a turbo decoder chip which can decode code rate k/(k + 1) constituent convolutional codes for k=1, 2, 4, 8, and 16. After replacing the constituent code by its code rate 1/(k + 1) reciprocal dual code, we can derive a smaller codeword space and design a simpler decoding trellis structure for high code-rate SISO decoder. In addition, two parallel SISO decoders are exploited in our turbo decoder by using the quadratic permutation polynomial (QPP) interleaver to improve the decoding speed. After fabricated in 1P9M CMOS 40 nm process, the proposed decoder with 1.27 mm2 core area can achieve 535 Mbps throughput at 8/9 code rate, and the energy efficiency is 0.068 nJ/bit/iteration at 0.9 V.",

author = "Lin, {Chen Yang} and Wong, {Cheng Chi} and Hsie-Chia Chang",

year = "2012",

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doi = "10.1109/IPEC.2012.6522659",

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N2 - This paper presents a turbo decoder chip which can decode code rate k/(k + 1) constituent convolutional codes for k=1, 2, 4, 8, and 16. After replacing the constituent code by its code rate 1/(k + 1) reciprocal dual code, we can derive a smaller codeword space and design a simpler decoding trellis structure for high code-rate SISO decoder. In addition, two parallel SISO decoders are exploited in our turbo decoder by using the quadratic permutation polynomial (QPP) interleaver to improve the decoding speed. After fabricated in 1P9M CMOS 40 nm process, the proposed decoder with 1.27 mm2 core area can achieve 535 Mbps throughput at 8/9 code rate, and the energy efficiency is 0.068 nJ/bit/iteration at 0.9 V.

AB - This paper presents a turbo decoder chip which can decode code rate k/(k + 1) constituent convolutional codes for k=1, 2, 4, 8, and 16. After replacing the constituent code by its code rate 1/(k + 1) reciprocal dual code, we can derive a smaller codeword space and design a simpler decoding trellis structure for high code-rate SISO decoder. In addition, two parallel SISO decoders are exploited in our turbo decoder by using the quadratic permutation polynomial (QPP) interleaver to improve the decoding speed. After fabricated in 1P9M CMOS 40 nm process, the proposed decoder with 1.27 mm2 core area can achieve 535 Mbps throughput at 8/9 code rate, and the energy efficiency is 0.068 nJ/bit/iteration at 0.9 V.

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A 40 nm 535 Mbps multiple code-rate turbo decoder chip using reciprocal dual trellis

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