This paper presents a turbo decoder chip which can decode code rate k/(k + 1) constituent convolutional codes for k=1, 2, 4, 8, and 16. After replacing the constituent code by its code rate 1/(k + 1) reciprocal dual code, we can derive a smaller codeword space and design a simpler decoding trellis structure for high code-rate SISO decoder. In addition, two parallel SISO decoders are exploited in our turbo decoder by using the quadratic permutation polynomial (QPP) interleaver to improve the decoding speed. After fabricated in 1P9M CMOS 40 nm process, the proposed decoder with 1.27 mm2 core area can achieve 535 Mbps throughput at 8/9 code rate, and the energy efficiency is 0.068 nJ/bit/iteration at 0.9 V.
|出版狀態||Published - 1 12月 2012|
|事件||2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan|
持續時間: 12 11月 2012 → 14 11月 2012
|Conference||2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012|
|期間||12/11/12 → 14/11/12|