A 40 nm 512 kb cross-point 8 T pipeline SRAM with binary word-line boosting control, ripple bit-line and adaptive data-aware write-assist

Nan Chun Lien, Li Wei Chu, Chien Hen Chen, Hao I. Yang, Ming Hsien Tu, Paul Sen Kan, Yong Jyun Hu, Ching Te Chuang, Shyh-Jye Jou, Wei Hwang

研究成果: Article同行評審

31 引文 斯高帕斯(Scopus)

摘要

This paper presents a cross-point 512 kb 8 T pipeline static random-access memory (SRAM). The cross-point structure eliminates write half-select disturb to facilitate bit-interleaving architecture for enhanced soft error immunity. The design employs boosted word-line (WL) for improving both read performance and write-ability. A ripple bit-line (RiBL) structure provides 30%-44% read access performance improvement and 2×-3.5× variation immunity at 0.7 V compared with the conventional hierarchical bit-line (HiBL) schemes. An adaptive data-aware write-assist (ADAWA) with VCS tracking is employed to further enhance the write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An adaptive voltage detector (AVD) with binary boosting control is used to mitigating gate electric over-stress. The design is implemented in UMC 40 nm low-power (40LP) CMOS technology. The 512 kb test chip operates from 1.5 V to 0.65 V, with maximum operation frequency of 800 MHz@1.1 V and 200 MHz@0.65 V. The measured power consumption is 0.5 mW/MHz (active) and 4.4 mW (standby) at 1.1 V, and 0.107 mW/MHz (active) and 0.367 mW (standby) at 0.65 V.

原文English
文章編號6891326
頁(從 - 到)3416-3425
頁數10
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
61
發行號12
DOIs
出版狀態Published - 1 1月 2014

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