A 40 nm 0.32 v 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist

Yi Wei Chiu; Yu Hao Hu; Ming Hsien Tu; Jun Kai Zhao; Shyh-Jye Jou; Ching Te Chuang

doi:10.1109/ISLPED.2013.6629266

A 40 nm 0.32 v 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist

Yi Wei Chiu, Yu Hao Hu, Ming Hsien Tu, Jun Kai Zhao, Shyh-Jye Jou, Ching Te Chuang

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研究成果: Conference contribution › 同行評審

18 引文斯高帕斯（Scopus）

摘要

This paper presents a new bit-interleaving 11T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to mitigate the leakage and variation and improve the Write-ability in deep sub-100nm technology. Measurement results from a 4 Kb test chip implemented in 40 nm General Purpose (40GP) CMOS technology operates for V_DD down to 0.32 V (∼0.69X of threshold voltage) with V_DDMIN limited by Read operation. The measured maximum operation frequency is 3.5 MHz (16.5 MHz) at 0.32 V (0.38 V) with total power consumption of 15.2 μW (27.2 μW) at 25 °C.

原文	English
主出版物標題	Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2013
頁面	51-56
頁數	6
DOIs	https://doi.org/10.1109/ISLPED.2013.6629266
出版狀態	Published - 11 12月 2013
事件	2013 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2013 - Beijing, China 持續時間: 4 9月 2013 → 6 9月 2013

出版系列

名字	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN（列印）	1533-4678

Conference

Conference	2013 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2013
國家/地區	China
城市	Beijing
期間	4/09/13 → 6/09/13

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10.1109/ISLPED.2013.6629266

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Link to publication in Scopus

引用此

Chiu, Y. W., Hu, Y. H., Tu, M. H., Zhao, J. K., Jou, S-J., & Chuang, C. T. (2013). A 40 nm 0.32 v 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. 於 Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2013 (頁 51-56). [6629266] (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1109/ISLPED.2013.6629266

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title = "A 40 nm 0.32 v 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist",

abstract = "This paper presents a new bit-interleaving 11T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to mitigate the leakage and variation and improve the Write-ability in deep sub-100nm technology. Measurement results from a 4 Kb test chip implemented in 40 nm General Purpose (40GP) CMOS technology operates for VDD down to 0.32 V (∼0.69X of threshold voltage) with VDDMIN limited by Read operation. The measured maximum operation frequency is 3.5 MHz (16.5 MHz) at 0.32 V (0.38 V) with total power consumption of 15.2 μW (27.2 μW) at 25 °C.",

author = "Chiu, {Yi Wei} and Hu, {Yu Hao} and Tu, {Ming Hsien} and Zhao, {Jun Kai} and Shyh-Jye Jou and Chuang, {Ching Te}",

year = "2013",

month = dec,

day = "11",

doi = "10.1109/ISLPED.2013.6629266",

language = "English",

isbn = "9781479912353",

series = "Proceedings of the International Symposium on Low Power Electronics and Design",

pages = "51--56",

booktitle = "Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2013",

note = "null ; Conference date: 04-09-2013 Through 06-09-2013",

}

Chiu, YW, Hu, YH, Tu, MH, Zhao, JK, Jou, S-J & Chuang, CT 2013, A 40 nm 0.32 v 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. 於 Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2013., 6629266, Proceedings of the International Symposium on Low Power Electronics and Design, 頁 51-56, 2013 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2013, Beijing, China, 4/09/13. https://doi.org/10.1109/ISLPED.2013.6629266

A 40 nm 0.32 v 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. / Chiu, Yi Wei; Hu, Yu Hao; Tu, Ming Hsien 等.

Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2013. 2013. p. 51-56 6629266 (Proceedings of the International Symposium on Low Power Electronics and Design).

研究成果: Conference contribution › 同行評審

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AU - Chiu, Yi Wei

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AU - Zhao, Jun Kai

AU - Jou, Shyh-Jye

AU - Chuang, Ching Te

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AB - This paper presents a new bit-interleaving 11T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to mitigate the leakage and variation and improve the Write-ability in deep sub-100nm technology. Measurement results from a 4 Kb test chip implemented in 40 nm General Purpose (40GP) CMOS technology operates for VDD down to 0.32 V (∼0.69X of threshold voltage) with VDDMIN limited by Read operation. The measured maximum operation frequency is 3.5 MHz (16.5 MHz) at 0.32 V (0.38 V) with total power consumption of 15.2 μW (27.2 μW) at 25 °C.

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Chiu YW, Hu YH, Tu MH, Zhao JK, Jou S-J, Chuang CT. A 40 nm 0.32 v 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. 於 Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2013. 2013. p. 51-56. 6629266. (Proceedings of the International Symposium on Low Power Electronics and Design). doi: 10.1109/ISLPED.2013.6629266

A 40 nm 0.32 v 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist

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