A 40 nm 0.32 v 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist

Yi Wei Chiu, Yu Hao Hu, Ming Hsien Tu, Jun Kai Zhao, Shyh-Jye Jou, Ching Te Chuang

研究成果: Conference contribution同行評審

20 引文 斯高帕斯(Scopus)

摘要

This paper presents a new bit-interleaving 11T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to mitigate the leakage and variation and improve the Write-ability in deep sub-100nm technology. Measurement results from a 4 Kb test chip implemented in 40 nm General Purpose (40GP) CMOS technology operates for VDD down to 0.32 V (∼0.69X of threshold voltage) with VDDMIN limited by Read operation. The measured maximum operation frequency is 3.5 MHz (16.5 MHz) at 0.32 V (0.38 V) with total power consumption of 15.2 μW (27.2 μW) at 25 °C.

原文English
主出版物標題Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2013
頁面51-56
頁數6
DOIs
出版狀態Published - 11 12月 2013
事件2013 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2013 - Beijing, China
持續時間: 4 9月 20136 9月 2013

出版系列

名字Proceedings of the International Symposium on Low Power Electronics and Design
ISSN(列印)1533-4678

Conference

Conference2013 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2013
國家/地區China
城市Beijing
期間4/09/136/09/13

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