A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking

Chia Tse Hung; Yu Ping Huang; Wei-Zen Chen

doi:10.1109/ASSCC.2018.8579300

A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking

Chia Tse Hung, Yu Ping Huang, Wei-Zen Chen

電子研究所

研究成果: Conference contribution › 同行評審

8 引文斯高帕斯（Scopus）

摘要

A 40 Gb/s PAM-4 receiver comprised of a continuous-time linear equalizer (CTLE) and 2-tap decision-feedback equalizers (DFE) based on a novel level tracking circuit (ANLT) is proposed. A sign-sign LMS engine is embedded for the DFE and ANLT coefficients adaptation to accommodate different channel loss. The ANLT is capable of automatically tracking a non-evenly spaced PAM-4 signal, allowing the receiver to demodulate a distorted input with 2-bit flash ADCs. Fabricated in a TSMC 40nm CMOS technology, the whole receiver consumes 241.8 mW at 40 Gb/s operation. Core area is 0.274mm ² .

原文	English
主出版物標題	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	213-214
頁數	2
ISBN（電子）	9781538664124
DOIs	https://doi.org/10.1109/ASSCC.2018.8579300
出版狀態	Published - 14 12月 2018
事件	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Tainan, 台灣持續時間: 5 11月 2018 → 7 11月 2018

出版系列

名字	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings

Conference

Conference	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018
國家/地區	台灣
城市	Tainan
期間	5/11/18 → 7/11/18

存取文件

10.1109/ASSCC.2018.8579300

其它文件與鏈接

Link to publication in Scopus

引用此

Hung, C. T., Huang, Y. P., & Chen, W.-Z. (2018). A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking. 於 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings (頁 213-214). 文章 8579300 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2018.8579300

@inproceedings{19831934b2924bb1b85f14e6acccbf58,

title = "A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking",

abstract = " A 40 Gb/s PAM-4 receiver comprised of a continuous-time linear equalizer (CTLE) and 2-tap decision-feedback equalizers (DFE) based on a novel level tracking circuit (ANLT) is proposed. A sign-sign LMS engine is embedded for the DFE and ANLT coefficients adaptation to accommodate different channel loss. The ANLT is capable of automatically tracking a non-evenly spaced PAM-4 signal, allowing the receiver to demodulate a distorted input with 2-bit flash ADCs. Fabricated in a TSMC 40nm CMOS technology, the whole receiver consumes 241.8 mW at 40 Gb/s operation. Core area is 0.274mm 2 . ",

keywords = "automatically non-even level tracking (ANLT), continuous-time linear equalizer (CTLE), decision-feedback equalizer (DFE), Pulse-amplitude modulation (PAM), sign-sign least mean square (SS-LMS)",

author = "Hung, {Chia Tse} and Huang, {Yu Ping} and Wei-Zen Chen",

year = "2018",

month = dec,

day = "14",

doi = "10.1109/ASSCC.2018.8579300",

language = "English",

series = "2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "213--214",

booktitle = "2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings",

address = "美國",

note = "2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 ; Conference date: 05-11-2018 Through 07-11-2018",

}

Hung, CT, Huang, YP & Chen, W-Z 2018, A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking. 於 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings., 8579300, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 頁 213-214, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, 台灣, 5/11/18. https://doi.org/10.1109/ASSCC.2018.8579300

A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking. / Hung, Chia Tse; Huang, Yu Ping; Chen, Wei-Zen.
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 213-214 8579300 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

研究成果: Conference contribution › 同行評審

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T1 - A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking

AU - Hung, Chia Tse

AU - Huang, Yu Ping

AU - Chen, Wei-Zen

PY - 2018/12/14

Y1 - 2018/12/14

N2 - A 40 Gb/s PAM-4 receiver comprised of a continuous-time linear equalizer (CTLE) and 2-tap decision-feedback equalizers (DFE) based on a novel level tracking circuit (ANLT) is proposed. A sign-sign LMS engine is embedded for the DFE and ANLT coefficients adaptation to accommodate different channel loss. The ANLT is capable of automatically tracking a non-evenly spaced PAM-4 signal, allowing the receiver to demodulate a distorted input with 2-bit flash ADCs. Fabricated in a TSMC 40nm CMOS technology, the whole receiver consumes 241.8 mW at 40 Gb/s operation. Core area is 0.274mm 2 .

AB - A 40 Gb/s PAM-4 receiver comprised of a continuous-time linear equalizer (CTLE) and 2-tap decision-feedback equalizers (DFE) based on a novel level tracking circuit (ANLT) is proposed. A sign-sign LMS engine is embedded for the DFE and ANLT coefficients adaptation to accommodate different channel loss. The ANLT is capable of automatically tracking a non-evenly spaced PAM-4 signal, allowing the receiver to demodulate a distorted input with 2-bit flash ADCs. Fabricated in a TSMC 40nm CMOS technology, the whole receiver consumes 241.8 mW at 40 Gb/s operation. Core area is 0.274mm 2 .

KW - automatically non-even level tracking (ANLT)

KW - continuous-time linear equalizer (CTLE)

KW - decision-feedback equalizer (DFE)

KW - Pulse-amplitude modulation (PAM)

KW - sign-sign least mean square (SS-LMS)

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M3 - Conference contribution

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T3 - 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings

SP - 213

EP - 214

BT - 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018

Y2 - 5 November 2018 through 7 November 2018

ER -

Hung CT, Huang YP, Chen WZ. A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking. 於 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 213-214. 8579300. (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings). doi: 10.1109/ASSCC.2018.8579300

A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking

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Conference

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