@inproceedings{19831934b2924bb1b85f14e6acccbf58,
title = "A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking",
abstract = " A 40 Gb/s PAM-4 receiver comprised of a continuous-time linear equalizer (CTLE) and 2-tap decision-feedback equalizers (DFE) based on a novel level tracking circuit (ANLT) is proposed. A sign-sign LMS engine is embedded for the DFE and ANLT coefficients adaptation to accommodate different channel loss. The ANLT is capable of automatically tracking a non-evenly spaced PAM-4 signal, allowing the receiver to demodulate a distorted input with 2-bit flash ADCs. Fabricated in a TSMC 40nm CMOS technology, the whole receiver consumes 241.8 mW at 40 Gb/s operation. Core area is 0.274mm 2 . ",
keywords = "automatically non-even level tracking (ANLT), continuous-time linear equalizer (CTLE), decision-feedback equalizer (DFE), Pulse-amplitude modulation (PAM), sign-sign least mean square (SS-LMS)",
author = "Hung, {Chia Tse} and Huang, {Yu Ping} and Wei-Zen Chen",
year = "2018",
month = dec,
day = "14",
doi = "10.1109/ASSCC.2018.8579300",
language = "English",
series = "2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "213--214",
booktitle = "2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings",
address = "United States",
note = "2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 ; Conference date: 05-11-2018 Through 07-11-2018",
}