A 40 Gbps optical receiver analog front-end in 65 nm CMOS

Shun Tien Chou; Shih Hao Huang; Zheng Hao Hong; Wei-Zen Chen

doi:10.1109/ISCAS.2012.6271598

A 40 Gbps optical receiver analog front-end in 65 nm CMOS

Shun Tien Chou^*, Shih Hao Huang, Zheng Hao Hong, Wei-Zen Chen

^*此作品的通信作者

研究成果: Paper › 同行評審

15 引文斯高帕斯（Scopus）

摘要

A 40 Gbps optical receiver analog front end integrating a trans-impedance amplifier (TIA) and a limiting amplifier is presented. To achieve wide band operation, nested feedback TIA and interleaving post amplifier with split series-peaking are proposed in this design. This receiver provides the transimpedance of 92 dBOhm, input-referred noise of 14 pA/Hz, 3dB bandwidth of 35 GHz, and 800mV _pp differential output voltage swing. The total power dissipation is 168 mW from 1.2-V supply. Fabricated in a 65 nm CMOS technology, the chip size is 0.825mm ².

原文	English
頁面	1736-1739
頁數	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271598
出版狀態	Published - 2012
事件	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of 持續時間: 20 5月 2012 → 23 5月 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
國家/地區	Korea, Republic of
城市	Seoul
期間	20/05/12 → 23/05/12

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10.1109/ISCAS.2012.6271598

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abstract = "A 40 Gbps optical receiver analog front end integrating a trans-impedance amplifier (TIA) and a limiting amplifier is presented. To achieve wide band operation, nested feedback TIA and interleaving post amplifier with split series-peaking are proposed in this design. This receiver provides the transimpedance of 92 dBOhm, input-referred noise of 14 pA/Hz, 3dB bandwidth of 35 GHz, and 800mV pp differential output voltage swing. The total power dissipation is 168 mW from 1.2-V supply. Fabricated in a 65 nm CMOS technology, the chip size is 0.825mm 2.",

author = "Chou, {Shun Tien} and Huang, {Shih Hao} and Hong, {Zheng Hao} and Wei-Zen Chen",

year = "2012",

doi = "10.1109/ISCAS.2012.6271598",

language = "English",

pages = "1736--1739",

note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

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AU - Chou, Shun Tien

AU - Huang, Shih Hao

AU - Hong, Zheng Hao

AU - Chen, Wei-Zen

PY - 2012

Y1 - 2012

N2 - A 40 Gbps optical receiver analog front end integrating a trans-impedance amplifier (TIA) and a limiting amplifier is presented. To achieve wide band operation, nested feedback TIA and interleaving post amplifier with split series-peaking are proposed in this design. This receiver provides the transimpedance of 92 dBOhm, input-referred noise of 14 pA/Hz, 3dB bandwidth of 35 GHz, and 800mV pp differential output voltage swing. The total power dissipation is 168 mW from 1.2-V supply. Fabricated in a 65 nm CMOS technology, the chip size is 0.825mm 2.

AB - A 40 Gbps optical receiver analog front end integrating a trans-impedance amplifier (TIA) and a limiting amplifier is presented. To achieve wide band operation, nested feedback TIA and interleaving post amplifier with split series-peaking are proposed in this design. This receiver provides the transimpedance of 92 dBOhm, input-referred noise of 14 pA/Hz, 3dB bandwidth of 35 GHz, and 800mV pp differential output voltage swing. The total power dissipation is 168 mW from 1.2-V supply. Fabricated in a 65 nm CMOS technology, the chip size is 0.825mm 2.

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U2 - 10.1109/ISCAS.2012.6271598

DO - 10.1109/ISCAS.2012.6271598

M3 - Paper

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T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012

Y2 - 20 May 2012 through 23 May 2012

ER -

A 40 Gbps optical receiver analog front-end in 65 nm CMOS

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