A 4-Mbit NAND-EEPROM with tight programmed Vt distribution

Tomoharu Tanaka; Masaki Momodomi; Yoshihisa Iwata; Yoshiyuki Tanaka; Hideko Oodaira; Yasuo Itoh; Shirota Riichiro; Kazunori Ohuchi; Fujio Masuoka

doi:10.1109/VLSIC.1990.111117

A 4-Mbit NAND-EEPROM with tight programmed V_t distribution

Tomoharu Tanaka^*, Masaki Momodomi, Yoshihisa Iwata, Yoshiyuki Tanaka, Hideko Oodaira, Yasuo Itoh, Shirota Riichiro, Kazunori Ohuchi, Fujio Masuoka

^*此作品的通信作者

電機工程學系

研究成果: Paper › 同行評審

15 引文斯高帕斯（Scopus）

摘要

The authors describe a 4-Mb NAND-EEPROM with tight V_t (threshold voltage) distribution which is controlled by a novel program verify technique. A tight V_t distribution width of 0.6 V for the entire 4-Mb cell array is achieved, and read margin is improved. A unique twin P-well structure has made it possible to realize low-power 5-V-only erase/program operation easily compared with the previous design.

原文	English
頁面	105-106
頁數	2
DOIs	https://doi.org/10.1109/VLSIC.1990.111117
出版狀態	Published - 6月 1990
事件	1990 Symposium on VLSI Circuits - Honolulu, HI, USA 持續時間: 7 6月 1990 → 9 6月 1990

Conference

Conference	1990 Symposium on VLSI Circuits
城市	Honolulu, HI, USA
期間	7/06/90 → 9/06/90

存取文件

10.1109/VLSIC.1990.111117

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Link to publication in Scopus

引用此

@conference{754d4f7a4d81473593dd53f134079dfd,

title = "A 4-Mbit NAND-EEPROM with tight programmed Vt distribution",

abstract = "The authors describe a 4-Mb NAND-EEPROM with tight Vt (threshold voltage) distribution which is controlled by a novel program verify technique. A tight Vt distribution width of 0.6 V for the entire 4-Mb cell array is achieved, and read margin is improved. A unique twin P-well structure has made it possible to realize low-power 5-V-only erase/program operation easily compared with the previous design.",

author = "Tomoharu Tanaka and Masaki Momodomi and Yoshihisa Iwata and Yoshiyuki Tanaka and Hideko Oodaira and Yasuo Itoh and Shirota Riichiro and Kazunori Ohuchi and Fujio Masuoka",

year = "1990",

month = jun,

doi = "10.1109/VLSIC.1990.111117",

language = "English",

pages = "105--106",

note = "1990 Symposium on VLSI Circuits ; Conference date: 07-06-1990 Through 09-06-1990",

}

TY - CONF

T1 - A 4-Mbit NAND-EEPROM with tight programmed Vt distribution

AU - Tanaka, Tomoharu

AU - Momodomi, Masaki

AU - Iwata, Yoshihisa

AU - Tanaka, Yoshiyuki

AU - Oodaira, Hideko

AU - Itoh, Yasuo

AU - Riichiro, Shirota

AU - Ohuchi, Kazunori

AU - Masuoka, Fujio

PY - 1990/6

Y1 - 1990/6

N2 - The authors describe a 4-Mb NAND-EEPROM with tight Vt (threshold voltage) distribution which is controlled by a novel program verify technique. A tight Vt distribution width of 0.6 V for the entire 4-Mb cell array is achieved, and read margin is improved. A unique twin P-well structure has made it possible to realize low-power 5-V-only erase/program operation easily compared with the previous design.

AB - The authors describe a 4-Mb NAND-EEPROM with tight Vt (threshold voltage) distribution which is controlled by a novel program verify technique. A tight Vt distribution width of 0.6 V for the entire 4-Mb cell array is achieved, and read margin is improved. A unique twin P-well structure has made it possible to realize low-power 5-V-only erase/program operation easily compared with the previous design.

UR - http://www.scopus.com/inward/record.url?scp=0025561716&partnerID=8YFLogxK

U2 - 10.1109/VLSIC.1990.111117

DO - 10.1109/VLSIC.1990.111117

M3 - Paper

AN - SCOPUS:0025561716

SP - 105

EP - 106

T2 - 1990 Symposium on VLSI Circuits

Y2 - 7 June 1990 through 9 June 1990

ER -

A 4-Mbit NAND-EEPROM with tight programmed Vt distribution

摘要

Conference

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引用此

A 4-Mbit NAND-EEPROM with tight programmed V_t distribution