Many big-data (BD) processors reduce power consumption by employing ternary content-addressable-memory (TCAM) [1-2] with pre-stored signature patterns as filters to reduce the amount of data sent for processing in the following stage (i.e., wireless transmission). To further reduce standby power, BD-processors commonly use nonvolatile memory (NVM) to back up the signature patterns of SRAM-based TCAM (sTCAM)  during power interruptions or frequent-off operations. However, this 2-macro (sTCAM + NVM) scheme suffers long delays and requires considerable energy for wake-up operations, due to the word-by-word serial transfer of data between NVM and TCAM macros. Most of the signature patterns are seldom updated (written); therefore, single-macro nonvolatile TCAM (nvTCAM) can be used for BD-processors to reduce area and facilitate fast/low-power wake-up operations, compared to the 2-macro approach. Previous nvTCAMs were designed using diode-connected 4T2R with STT-MTJ (D4T2R) , 2T2R with PCM , and 4T2R with ReRAM ; however, they suffer the following issues: (1) large cell area (A) and high write energy (Ew) due to the use of two NVM (2R) devices; (2) limited word-length (WDL, /k-bits) caused by small current-ratio (I-ratio= IML-MIS/(K×IML)) between match-line (ML) mismatch current (IML-MIS) and ML leakage current of k matched cells (k × IML-MIS); (3) Long search delays (TSD) and excessive search energy (Es) due to large ML parasitic load (CML) and small I-ratio. ReRAM is promising for nvTCAM due to its low Ew, high resistance-ratio (R-ratio), and multiple-level cell (MLC) capability. To overcome issue (1) to (3), this study develops an MLC-based 3T1R nvTCAM with bi-directional voltage-divider control (BVDC). A 2×64×64b 3T1R nvTCAM macro is fabricated using back-end-of-line (BEOL) ReRAM  and a 90nm CMOS process, with 2.27× cell size reduction as compared with sTCAM using the same technology and the TSD (=0.96ns) for WDL=64b.