A 3.84 Gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology

Alireza Hodjat; David D. Hwang; Bo-Cheng Lai; Kris Tiri; Ingrid Verbauwhede

doi:10.1145/1057661.1057677

A 3.84 Gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology

Alireza Hodjat^*, David D. Hwang, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede

^*此作品的通信作者

電子研究所

研究成果: Paper › 同行評審

61 引文斯高帕斯（Scopus）

摘要

In this paper an AES crypto coprocessor that is fabricated using a 0.18-μm CMOS technology is presented. This crypto coprocessor performs the AES-128 encryption in both feedback and non-feedback modes of operation. A maximum throughput of 3.84 Gbits/s is achieved at a 330 MHz clock frequency for ECB, OFB, and CBC modes of operation. This crypto coprocessor can be programmed using the memory-mapped interface of an embedded CPU core and is tested using a LEON 32-bit (SPARC V8) processor in the ThumbPod secure system-on-chip.

原文	English
頁面	60-63
頁數	4
DOIs	https://doi.org/10.1145/1057661.1057677
出版狀態	Published - 29 12月 2005
事件	2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, 美國持續時間: 17 4月 2005 → 19 4月 2005

Conference

Conference	2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05
國家/地區	美國
城市	Chicago, IL
期間	17/04/05 → 19/04/05

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10.1145/1057661.1057677

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引用此

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author = "Alireza Hodjat and Hwang, {David D.} and Bo-Cheng Lai and Kris Tiri and Ingrid Verbauwhede",

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AU - Tiri, Kris

AU - Verbauwhede, Ingrid

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A 3.84 Gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology

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