In this paper an AES crypto coprocessor that is fabricated using a 0.18-μm CMOS technology is presented. This crypto coprocessor performs the AES-128 encryption in both feedback and non-feedback modes of operation. A maximum throughput of 3.84 Gbits/s is achieved at a 330 MHz clock frequency for ECB, OFB, and CBC modes of operation. This crypto coprocessor can be programmed using the memory-mapped interface of an embedded CPU core and is tested using a LEON 32-bit (SPARC V8) processor in the ThumbPod secure system-on-chip.
|出版狀態||Published - 29 12月 2005|
|事件||2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, United States|
持續時間: 17 4月 2005 → 19 4月 2005
|Conference||2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05|
|期間||17/04/05 → 19/04/05|