A 3.84 Gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology

Alireza Hodjat*, David D. Hwang, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede

*此作品的通信作者

研究成果: Paper同行評審

50 引文 斯高帕斯(Scopus)

摘要

In this paper an AES crypto coprocessor that is fabricated using a 0.18-μm CMOS technology is presented. This crypto coprocessor performs the AES-128 encryption in both feedback and non-feedback modes of operation. A maximum throughput of 3.84 Gbits/s is achieved at a 330 MHz clock frequency for ECB, OFB, and CBC modes of operation. This crypto coprocessor can be programmed using the memory-mapped interface of an embedded CPU core and is tested using a LEON 32-bit (SPARC V8) processor in the ThumbPod secure system-on-chip.

原文English
頁面60-63
頁數4
DOIs
出版狀態Published - 29 十二月 2005
事件2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, United States
持續時間: 17 四月 200519 四月 2005

Conference

Conference2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05
國家/地區United States
城市Chicago, IL
期間17/04/0519/04/05

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