A 3.5-ns/77 K and 6.2-ns/300 K 64K CMOS RAM with ECL Interfaces

Terry I. Chappell; Stanley E. Schuster; Barbara A. Chappell; James W. Allan; Jack Y.C. Sun; Stephen P. Klepner; Robert L. Franch; Paul F. Greier; Phillip J. Restle

doi:10.1109/4.34062

A 3.5-ns/77 K and 6.2-ns/300 K 64K CMOS RAM with ECL Interfaces

Terry I. Chappell, Stanley E. Schuster, Barbara A. Chappell, James W. Allan, Jack Y.C. Sun, Stephen P. Klepner, Robert L. Franch, Paul F. Greier, Phillip J. Restle

國際半導體產業學院

研究成果: Article › 同行評審

7 引文斯高帕斯（Scopus）

摘要

This paper describes a 64K CMOS RAM with ECL interfaces having access times of 6.2 ns at room temperature and, with a CMOS process specifically optimized for low-temperature operation, 3.5 ns at liquid nitrogen (LN) temperature. The CMOS processes feature a 0.5-μm L_ett, self-aligned TiSi₂, double-level metal, and an average minimum feature size of 1.35 μm. Circuits key to high-speed operation are described with emphasis on low power and safe operation. Unique aspects of LN-temperature operation are discussed including circuit/device interactions, the impact of velocity saturation effects on channel length, temperature and power supply sensitivities, and the characteristics of the ECL-to-CMOS receiver circuits.

原文	English
頁（從 - 到）	859-868
頁數	10
期刊	IEEE Journal of Solid-State Circuits
卷	24
發行號	4
DOIs	https://doi.org/10.1109/4.34062
出版狀態	Published - 8月 1989

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10.1109/4.34062

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title = "A 3.5-ns/77 K and 6.2-ns/300 K 64K CMOS RAM with ECL Interfaces",

abstract = "This paper describes a 64K CMOS RAM with ECL interfaces having access times of 6.2 ns at room temperature and, with a CMOS process specifically optimized for low-temperature operation, 3.5 ns at liquid nitrogen (LN) temperature. The CMOS processes feature a 0.5-μm Lett, self-aligned TiSi2, double-level metal, and an average minimum feature size of 1.35 μm. Circuits key to high-speed operation are described with emphasis on low power and safe operation. Unique aspects of LN-temperature operation are discussed including circuit/device interactions, the impact of velocity saturation effects on channel length, temperature and power supply sensitivities, and the characteristics of the ECL-to-CMOS receiver circuits.",

author = "Chappell, {Terry I.} and Schuster, {Stanley E.} and Chappell, {Barbara A.} and Allan, {James W.} and Sun, {Jack Y.C.} and Klepner, {Stephen P.} and Franch, {Robert L.} and Greier, {Paul F.} and Restle, {Phillip J.}",

year = "1989",

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doi = "10.1109/4.34062",

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AU - Chappell, Terry I.

AU - Schuster, Stanley E.

AU - Chappell, Barbara A.

AU - Allan, James W.

AU - Sun, Jack Y.C.

AU - Klepner, Stephen P.

AU - Franch, Robert L.

AU - Greier, Paul F.

AU - Restle, Phillip J.

PY - 1989/8

Y1 - 1989/8

N2 - This paper describes a 64K CMOS RAM with ECL interfaces having access times of 6.2 ns at room temperature and, with a CMOS process specifically optimized for low-temperature operation, 3.5 ns at liquid nitrogen (LN) temperature. The CMOS processes feature a 0.5-μm Lett, self-aligned TiSi2, double-level metal, and an average minimum feature size of 1.35 μm. Circuits key to high-speed operation are described with emphasis on low power and safe operation. Unique aspects of LN-temperature operation are discussed including circuit/device interactions, the impact of velocity saturation effects on channel length, temperature and power supply sensitivities, and the characteristics of the ECL-to-CMOS receiver circuits.

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A 3.5-ns/77 K and 6.2-ns/300 K 64K CMOS RAM with ECL Interfaces

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