A 3.5-ns/77 K and 6.2-ns/300 K 64K CMOS RAM with ECL Interfaces

Terry I. Chappell, Stanley E. Schuster, Barbara A. Chappell, James W. Allan, Jack Y.C. Sun, Stephen P. Klepner, Robert L. Franch, Paul F. Greier, Phillip J. Restle

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7 引文 斯高帕斯(Scopus)

摘要

This paper describes a 64K CMOS RAM with ECL interfaces having access times of 6.2 ns at room temperature and, with a CMOS process specifically optimized for low-temperature operation, 3.5 ns at liquid nitrogen (LN) temperature. The CMOS processes feature a 0.5-μm Lett, self-aligned TiSi2, double-level metal, and an average minimum feature size of 1.35 μm. Circuits key to high-speed operation are described with emphasis on low power and safe operation. Unique aspects of LN-temperature operation are discussed including circuit/device interactions, the impact of velocity saturation effects on channel length, temperature and power supply sensitivities, and the characteristics of the ECL-to-CMOS receiver circuits.

原文English
頁(從 - 到)859-868
頁數10
期刊IEEE Journal of Solid-State Circuits
24
發行號4
DOIs
出版狀態Published - 8月 1989

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