A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer

Wei-Zen Chen; Shih Hao Huang; Guo Wei Wu; Chuan Chang Liu; Yang Tung Huang; Chin Fong Chiu; Wen Hsu Chang; Ying Zong Juang

doi:10.1109/ASSCC.2007.4425714

A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer

Wei-Zen Chen^*, Shih Hao Huang, Guo Wei Wu, Chuan Chang Liu, Yang Tung Huang, Chin Fong Chiu, Wen Hsu Chang, Ying Zong Juang

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

50 引文斯高帕斯（Scopus）

摘要

This paper presents the design of a 3.125 Gbps monolithic CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. The optical receiver is capable of delivering 420 mV^pp to 50 Ω output load after optical to electrical conversion. High speed operation is achieved by utilizing spatial modulated light (SML) detector and adaptive analog equalizer. Implemented in a 0.18 ?m CMOS technology, the total power dissipation is 175 mW. The chip size is 0.7 mm².

原文	English
主出版物標題	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
頁面	396-399
頁數	4
DOIs	https://doi.org/10.1109/ASSCC.2007.4425714
出版狀態	Published - 1 12月 2007
事件	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of 持續時間: 12 11月 2007 → 14 11月 2007

出版系列

名字	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Conference

Conference	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
國家/地區	Korea, Republic of
城市	Jeju
期間	12/11/07 → 14/11/07

存取文件

10.1109/ASSCC.2007.4425714

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Link to publication in Scopus

引用此

Chen, W.-Z., Huang, S. H., Wu, G. W., Liu, C. C., Huang, Y. T., Chiu, C. F., Chang, W. H., & Juang, Y. Z. (2007). A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer. 於 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC (頁 396-399). 文章 4425714 (2007 IEEE Asian Solid-State Circuits Conference, A-SSCC). https://doi.org/10.1109/ASSCC.2007.4425714

@inproceedings{fb9af428b6b84fce8d36407137cf05ba,

title = "A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer",

abstract = "This paper presents the design of a 3.125 Gbps monolithic CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. The optical receiver is capable of delivering 420 mVpp to 50 Ω output load after optical to electrical conversion. High speed operation is achieved by utilizing spatial modulated light (SML) detector and adaptive analog equalizer. Implemented in a 0.18 ?m CMOS technology, the total power dissipation is 175 mW. The chip size is 0.7 mm2.",

author = "Wei-Zen Chen and Huang, {Shih Hao} and Wu, {Guo Wei} and Liu, {Chuan Chang} and Huang, {Yang Tung} and Chiu, {Chin Fong} and Chang, {Wen Hsu} and Juang, {Ying Zong}",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/ASSCC.2007.4425714",

language = "English",

isbn = "1424413605",

series = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC",

pages = "396--399",

booktitle = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC",

note = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC ; Conference date: 12-11-2007 Through 14-11-2007",

}

Chen, W-Z, Huang, SH, Wu, GW, Liu, CC, Huang, YT, Chiu, CF, Chang, WH & Juang, YZ 2007, A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer. 於 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC., 4425714, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, 頁 396-399, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, Jeju, Korea, Republic of, 12/11/07. https://doi.org/10.1109/ASSCC.2007.4425714

TY - GEN

T1 - A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer

AU - Chen, Wei-Zen

AU - Huang, Shih Hao

AU - Wu, Guo Wei

AU - Liu, Chuan Chang

AU - Huang, Yang Tung

AU - Chiu, Chin Fong

AU - Chang, Wen Hsu

AU - Juang, Ying Zong

PY - 2007/12/1

Y1 - 2007/12/1

N2 - This paper presents the design of a 3.125 Gbps monolithic CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. The optical receiver is capable of delivering 420 mVpp to 50 Ω output load after optical to electrical conversion. High speed operation is achieved by utilizing spatial modulated light (SML) detector and adaptive analog equalizer. Implemented in a 0.18 ?m CMOS technology, the total power dissipation is 175 mW. The chip size is 0.7 mm2.

AB - This paper presents the design of a 3.125 Gbps monolithic CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. The optical receiver is capable of delivering 420 mVpp to 50 Ω output load after optical to electrical conversion. High speed operation is achieved by utilizing spatial modulated light (SML) detector and adaptive analog equalizer. Implemented in a 0.18 ?m CMOS technology, the total power dissipation is 175 mW. The chip size is 0.7 mm2.

UR - http://www.scopus.com/inward/record.url?scp=51349095090&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2007.4425714

DO - 10.1109/ASSCC.2007.4425714

M3 - Conference contribution

AN - SCOPUS:51349095090

SN - 1424413605

SN - 9781424413607

T3 - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

SP - 396

EP - 399

BT - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

T2 - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Y2 - 12 November 2007 through 14 November 2007

ER -

A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer

摘要

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Conference

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