@inproceedings{0c6d3dc403644879ab6cf8be0cb75692,
title = "A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery",
abstract = "A 19-27-Gb/s receiver comprising of a continuous time linear equalizer (CTLE) followed by a 2 tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broad band PLL to facilitate ISI and jitter suppression over wide band operation. A quadrature relaxation type oscillator is proposed to provide the sampling phases without bulky inductors. Fabricated in a 40 nm CMOS technology, the whole receiver manifests a high energy efficiency of 3.12pJ/bit at 27 Gbps operation to compensate 20 dB channel loss at Nyquist frequency. The core area is 0.09 mm2 only.",
keywords = "CDR, CTLE, DFE, PLL",
author = "Hong, {Zheng Hao} and Wei-Zen Chen",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 ; Conference date: 10-11-2014 Through 12-11-2014",
year = "2014",
month = nov,
day = "10",
doi = "10.1109/ASSCC.2014.7008914",
language = "English",
series = "2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "277--280",
booktitle = "2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers",
address = "United States",
}
