TY - JOUR
T1 - A 3-10 GHz, 14 bands CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system
AU - Lu, Tai You
AU - Chen, Wei-Zen
PY - 2012/5/1
Y1 - 2012/5/1
N2 - This paper presents the design of a 14 bands CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system. Based on a single phase-locked loop and two-stage frequency mixing architecture, it alleviates harmonics mixing and frequency pulling to diminish spurs generation. Also, only divide-by-2 dividers are needed in the feedback path of the PLL. Thus more precise I/Q sub-harmonics can be derived for the SSB mixer in the 14 bands carrier generation. The image spurs are suppressed below -45 dBc and improved by more than 22 dB incorporating with I/Q calibration. Implemented in a 0.18-μm CMOS technology, this chip drains 65 mA from a single 1.8 V supply. The chip size is 2.5 by 2.2 mm 2 providing 14 bands I/Q phases.
AB - This paper presents the design of a 14 bands CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system. Based on a single phase-locked loop and two-stage frequency mixing architecture, it alleviates harmonics mixing and frequency pulling to diminish spurs generation. Also, only divide-by-2 dividers are needed in the feedback path of the PLL. Thus more precise I/Q sub-harmonics can be derived for the SSB mixer in the 14 bands carrier generation. The image spurs are suppressed below -45 dBc and improved by more than 22 dB incorporating with I/Q calibration. Implemented in a 0.18-μm CMOS technology, this chip drains 65 mA from a single 1.8 V supply. The chip size is 2.5 by 2.2 mm 2 providing 14 bands I/Q phases.
KW - Frequency synthesizer
KW - I/Q calibration
KW - multi-band orthogonal frequency division multiplexing (MB-OFDM) ultra-wide band (UWB)
KW - phase-locked loop (PLL)
KW - single-side band (SSB) mixer
UR - http://www.scopus.com/inward/record.url?scp=84859792985&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2011.2134874
DO - 10.1109/TVLSI.2011.2134874
M3 - Article
AN - SCOPUS:84859792985
SN - 1063-8210
VL - 20
SP - 948
EP - 958
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 5
M1 - 5756216
ER -