An OFDM baseband receiver chip for DVB-T/H application is proposed In this paper. With all-digital jointed detection/synchronization loops and channel estimation, the proposed receiver chip can compensate 200ppm sampling clock offset (SCO) and ± 50 subcarrier spacing carrier frequency offset (CFO) In multipath environment. The total memory requirement of this chip is 102.8KB and the total equivalent gate count (Including memory) is about 806,800 gates. By using 0.18μm CMOS process, the power consumption is 28mW at 1.45 V, 40MHz and core size of this chip is 3600μm × 3600μm.
|頁（從 - 到）||351-354|
|期刊||Proceedings of the Custom Integrated Circuits Conference|
|出版狀態||Published - 26 12月 2008|
|事件||IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States|
持續時間: 21 9月 2008 → 24 9月 2008