A 26.9K 314.5Mbps soft (32400, 32208) BCH decoder chip for DVB-S2 system

Yi Min Lin; Chih Lung Chen; Hsie-Chia Chang; Chen-Yi Lee

doi:10.1109/ASSCC.2009.5357174

A 26.9K 314.5Mbps soft (32400, 32208) BCH decoder chip for DVB-S2 system

Yi Min Lin^*, Chih Lung Chen^*, Hsie-Chia Chang, Chen-Yi Lee

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

This paper provides a soft BCH decoder using error magnitudes to deal with least reliable bits. With soft information from the previous decoder defined in digital video broadcasting (DVB), the proposed soft BCH decoder provides much lower complexity and latency than the traditional hard BCH decoder while still maintaining performance. The proposed error locator evaluator architecture evaluates error locations without Chien search, leading to high throughput. Börck-Pereyra error magnitudes solvers (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The experimental result reveals that our proposed soft (32400, 32208) BCH decoder defined in DVB-S2 system can save 50.0% gate-count and achieve 314.5Mbps in standard CMOS 90nm technology.

原文	English
主出版物標題	Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
頁面	373-376
頁數	4
DOIs	https://doi.org/10.1109/ASSCC.2009.5357174
出版狀態	Published - 2009
事件	2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 - Taipei, Taiwan 持續時間: 16 11月 2009 → 18 11月 2009

出版系列

名字	Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Conference

Conference	2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
國家/地區	Taiwan
城市	Taipei
期間	16/11/09 → 18/11/09

存取文件

10.1109/ASSCC.2009.5357174

其它文件與鏈接

Link to publication in Scopus

引用此

Lin, Y. M., Chen, C. L., Chang, H.-C., & Lee, C.-Y. (2009). A 26.9K 314.5Mbps soft (32400, 32208) BCH decoder chip for DVB-S2 system. 於 Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 (頁 373-376). 文章 5357174 (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009). https://doi.org/10.1109/ASSCC.2009.5357174

@inproceedings{51138e1dae59421a872cd266adcf1d88,

title = "A 26.9K 314.5Mbps soft (32400, 32208) BCH decoder chip for DVB-S2 system",

abstract = "This paper provides a soft BCH decoder using error magnitudes to deal with least reliable bits. With soft information from the previous decoder defined in digital video broadcasting (DVB), the proposed soft BCH decoder provides much lower complexity and latency than the traditional hard BCH decoder while still maintaining performance. The proposed error locator evaluator architecture evaluates error locations without Chien search, leading to high throughput. B{\"o}rck-Pereyra error magnitudes solvers (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The experimental result reveals that our proposed soft (32400, 32208) BCH decoder defined in DVB-S2 system can save 50.0% gate-count and achieve 314.5Mbps in standard CMOS 90nm technology.",

keywords = "Bose-Chaudhuri-Hochquenghem (BCH) codes, Digital video broadcasting, Error correction coding",

author = "Lin, {Yi Min} and Chen, {Chih Lung} and Hsie-Chia Chang and Chen-Yi Lee",

year = "2009",

doi = "10.1109/ASSCC.2009.5357174",

language = "English",

isbn = "9781424444342",

series = "Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009",

pages = "373--376",

booktitle = "Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009",

note = "2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 ; Conference date: 16-11-2009 Through 18-11-2009",

}

Lin, YM, Chen, CL, Chang, H-C & Lee, C-Y 2009, A 26.9K 314.5Mbps soft (32400, 32208) BCH decoder chip for DVB-S2 system. 於 Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009., 5357174, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009, 頁 373-376, 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009, Taipei, Taiwan, 16/11/09. https://doi.org/10.1109/ASSCC.2009.5357174

A 26.9K 314.5Mbps soft (32400, 32208) BCH decoder chip for DVB-S2 system. / Lin, Yi Min; Chen, Chih Lung; Chang, Hsie-Chia 等.
Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. 2009. p. 373-376 5357174 (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009).

研究成果: Conference contribution › 同行評審

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T1 - A 26.9K 314.5Mbps soft (32400, 32208) BCH decoder chip for DVB-S2 system

AU - Lin, Yi Min

AU - Chen, Chih Lung

AU - Chang, Hsie-Chia

AU - Lee, Chen-Yi

PY - 2009

Y1 - 2009

N2 - This paper provides a soft BCH decoder using error magnitudes to deal with least reliable bits. With soft information from the previous decoder defined in digital video broadcasting (DVB), the proposed soft BCH decoder provides much lower complexity and latency than the traditional hard BCH decoder while still maintaining performance. The proposed error locator evaluator architecture evaluates error locations without Chien search, leading to high throughput. Börck-Pereyra error magnitudes solvers (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The experimental result reveals that our proposed soft (32400, 32208) BCH decoder defined in DVB-S2 system can save 50.0% gate-count and achieve 314.5Mbps in standard CMOS 90nm technology.

AB - This paper provides a soft BCH decoder using error magnitudes to deal with least reliable bits. With soft information from the previous decoder defined in digital video broadcasting (DVB), the proposed soft BCH decoder provides much lower complexity and latency than the traditional hard BCH decoder while still maintaining performance. The proposed error locator evaluator architecture evaluates error locations without Chien search, leading to high throughput. Börck-Pereyra error magnitudes solvers (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The experimental result reveals that our proposed soft (32400, 32208) BCH decoder defined in DVB-S2 system can save 50.0% gate-count and achieve 314.5Mbps in standard CMOS 90nm technology.

KW - Bose-Chaudhuri-Hochquenghem (BCH) codes

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KW - Error correction coding

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M3 - Conference contribution

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T3 - Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

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BT - Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

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A 26.9K 314.5Mbps soft (32400, 32208) BCH decoder chip for DVB-S2 system

摘要

出版系列

Conference

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其它文件與鏈接

指紋

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