A 25 Gb/s 1.13 pJ/b -10.8 dBm Input Sensitivity Optical Receiver in 40 nm CMOS

Shih Hao Huang, Wei-Zen Chen

研究成果: Article同行評審

32 引文 斯高帕斯(Scopus)


This paper describes the design of a 25 Gb/s energy-efficient CMOS optical receiver with high input sensitivity. By incorporating a current-boosting preamplifier with a dual-path time-interleaved integrating-type optical receiver, it provides 1:2 demultiplexing operation with a tolerance to lower bandwidth photodiodes. The bandwidth of current amplifier is chosen as 0.35× operating data rate for maximizing the receiver signal-to-noise ratio. Experimental results show that the receiver can achieve 25 Gb/s operation when integrated with a 9 or 17 GHz GaAs photodiode. Input sensitivities in the two cases are -7.2 dBm (w/i a 9 GHz photodiode) and -10.8 dBm (w/i a 17 GHz photodiode), respectively, for a bit error rate of less than 10-12. In addition, a single-tap decision-feedback equalizer (DFE) is embedded to compensate photodiode bandwidth and improve input sensitivity. Integrated with a low-cost 9 GHz photodiode, the input sensitivity and timing margin of the receiver are improved by 2 dB and 0.25 UI, respectively, after DFE compensation. By utilizing a current integrator and time-interleaved comparators, its energy efficiency is 1.13 pJ/b at 25 Gb/s under a 1.2 V power supply. Fabricated in a 40 nm bulk-CMOS technology, the core circuit occupies a chip area of 0.007 mm2 only.

頁(從 - 到)747-756
期刊IEEE Journal of Solid-State Circuits
出版狀態Published - 1 3月 2017


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