A 25-Gb/s, -10.8-dBm input sensitivity, PD-bandwidth tolerant CMOS optical receiver

Shih Hao Huang, Wei-Zen Chen

研究成果: Conference contribution同行評審

5 引文 斯高帕斯(Scopus)

摘要

This paper describes a 25-Gb/s energy-efficient CMOS optical receiver with high input sensitivity. By incorporating a current boosting preamplifier with time-interleaved integrating-type optical receiver, it also circumvents CID issue with high PD bandwidth tolerance. Experimental results show that the receiver can achieve 25-Gb/s operation by integrating with a 9-GHz or 17-GHz GaAs PD. Input sensitivities in the two cases are -7.2 dBm (w/i 9-GHz PD) and -10.8 dBm (w/i 17-GHz PD) respectively for BER of less than 10-12. The energy efficiency is 1.13 pJ/bit. Fabricated in TSMC 40-nm CMOS technology, the core circuit occupies a chip area of 0.007 mm2 only.

原文English
主出版物標題2015 Symposium on VLSI Circuits, VLSI Circuits 2015
發行者Institute of Electrical and Electronics Engineers Inc.
頁面C120-C121
ISBN(電子)9784863485020
DOIs
出版狀態Published - 31 8月 2015
事件29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 - Kyoto, Japan
持續時間: 17 6月 201519 6月 2015

出版系列

名字IEEE Symposium on VLSI Circuits, Digest of Technical Papers
2015-August

Conference

Conference29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
國家/地區Japan
城市Kyoto
期間17/06/1519/06/15

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