A 2.5 Gbps CMOS optical receiver analog front-end

Wei-Zen Chen; Chao Hsin Lu

doi:10.1109/CICC.2002.1012842

A 2.5 Gbps CMOS optical receiver analog front-end

Wei-Zen Chen, Chao Hsin Lu

電子研究所

研究成果: Article › 同行評審

38 引文斯高帕斯（Scopus）

摘要

A 3 V, single chip optical receiver analog front-end capable of operating at 2.5 Gbit/sec is fabricated in a 0.35 μ m CMOS technology. The IC contains a TIA with 54.5 dBΩ conversion gain, f _-3dB of 2.5 GHz, and a limiting amplifier with a conversion gain of 42 dB, f _-3db of 2.3 GHz. The TIA is DC coupled to the limiting amplifier. The measured eye diagram meet OC-48 transition mask. Input referred noise current is about 800 nA.

原文	English
頁（從 - 到）	359-362
頁數	4
期刊	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.2002.1012842
出版狀態	Published - 1 1月 2002

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A 2.5 Gbps CMOS optical receiver analog front-end

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