A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided Devices

Yu Chi Lee, Tai Shih Chi, Chia Hsiang Yang

研究成果: Conference contribution同行評審

6 引文 斯高帕斯(Scopus)

摘要

This paper proposes an acoustic DSP processor with a neural network core for speech enhancement. Accelerators for convolutional neural network (CNN) and fast Fourier transform (FFT) are embedded. The CNN-based speech enhancement algorithm takes the speech signals spectrogram as the model's input, and predicts the desired mask of speech to enhance speech intelligibility after passing through the CNN model. An array of multiply-accumulator (MAC) and coordinate rotation digital computer (CORDIC) engines are deployed to efficiently compute linear and nonlinear functions. Hardware sharing is applied to reduce hardware area by leveraging the high similarity between CNN and FFT computations. The proposed DSP processor chip is fabricated in a 40-nm CMOS technology with a core area of 4.3 mm2. The chip's power dissipation is 2.17 mW at an operating frequency of 5 MHz. The CNN accelerator supports both convolutional and fully-connected layers and achieves an energy efficiency of 1200-to-2180 GOPS/W, despite the flexibility for FFT. The speech intelligibility can be enhanced by up to 41% under low SNR conditions.

原文English
主出版物標題Proceedings 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019
發行者Institute of Electrical and Electronics Engineers Inc.
頁面97-101
頁數5
ISBN(電子)9781538678848
DOIs
出版狀態Published - 3月 2019
事件1st IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019 - Hsinchu, Taiwan
持續時間: 18 3月 201920 3月 2019

出版系列

名字Proceedings 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019

Conference

Conference1st IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019
國家/地區Taiwan
城市Hsinchu
期間18/03/1920/03/19

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