A 20-Gb/s optical receiver with integrated photo detector in 40-nm CMOS

Shih Hao Huang; Wei-Zen Chen

doi:10.1109/ASSCC.2013.6691023

A 20-Gb/s optical receiver with integrated photo detector in 40-nm CMOS

Shih Hao Huang, Wei-Zen Chen

電子研究所

研究成果: Conference contribution › 同行評審

10 引文斯高帕斯（Scopus）

摘要

This paper presents a 20-Gb/s monolithically integrated CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. Incorporating a 2-D meshed spatially-modulated light detector, the optical receiver achieves a record-high speed and is capable of delivering 80-dBΩ conversion gain when driving 50-Ω output loads. Nested-feedback topologies are adopted for transimpedance and post limiting amplifier design to achieve broad-band and high-gain operations without shunt-peaking inductors. Implemented in a generic 40-nm CMOS technology, the chip size is 0.6 × 0.54 mm². This receiver core drains 30 mW from 1-V supply.

原文	English
主出版物標題	Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
頁面	225-228
頁數	4
DOIs	https://doi.org/10.1109/ASSCC.2013.6691023
出版狀態	Published - 2013
事件	2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 - Singapore, Singapore 持續時間: 11 11月 2013 → 13 11月 2013

出版系列

名字	Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

Conference

Conference	2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
國家/地區	Singapore
城市	Singapore
期間	11/11/13 → 13/11/13

存取文件

10.1109/ASSCC.2013.6691023

其它文件與鏈接

Link to publication in Scopus

引用此

@inproceedings{478e27ee87b14e05a760486a4e33507e,

title = "A 20-Gb/s optical receiver with integrated photo detector in 40-nm CMOS",

abstract = "This paper presents a 20-Gb/s monolithically integrated CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. Incorporating a 2-D meshed spatially-modulated light detector, the optical receiver achieves a record-high speed and is capable of delivering 80-dBΩ conversion gain when driving 50-Ω output loads. Nested-feedback topologies are adopted for transimpedance and post limiting amplifier design to achieve broad-band and high-gain operations without shunt-peaking inductors. Implemented in a generic 40-nm CMOS technology, the chip size is 0.6 × 0.54 mm2. This receiver core drains 30 mW from 1-V supply.",

keywords = "OEIC, Optical Receiver, Photo Detector (PD), Transimpedance Amplifier (TIA)",

author = "Huang, {Shih Hao} and Wei-Zen Chen",

year = "2013",

doi = "10.1109/ASSCC.2013.6691023",

language = "English",

isbn = "9781479902781",

series = "Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013",

pages = "225--228",

booktitle = "Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013",

note = "2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 ; Conference date: 11-11-2013 Through 13-11-2013",

}

Huang, SH & Chen, W-Z 2013, A 20-Gb/s optical receiver with integrated photo detector in 40-nm CMOS. 於 Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013., 6691023, Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, 頁 225-228, 2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, Singapore, Singapore, 11/11/13. https://doi.org/10.1109/ASSCC.2013.6691023

TY - GEN

T1 - A 20-Gb/s optical receiver with integrated photo detector in 40-nm CMOS

AU - Huang, Shih Hao

AU - Chen, Wei-Zen

PY - 2013

Y1 - 2013

N2 - This paper presents a 20-Gb/s monolithically integrated CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. Incorporating a 2-D meshed spatially-modulated light detector, the optical receiver achieves a record-high speed and is capable of delivering 80-dBΩ conversion gain when driving 50-Ω output loads. Nested-feedback topologies are adopted for transimpedance and post limiting amplifier design to achieve broad-band and high-gain operations without shunt-peaking inductors. Implemented in a generic 40-nm CMOS technology, the chip size is 0.6 × 0.54 mm2. This receiver core drains 30 mW from 1-V supply.

AB - This paper presents a 20-Gb/s monolithically integrated CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. Incorporating a 2-D meshed spatially-modulated light detector, the optical receiver achieves a record-high speed and is capable of delivering 80-dBΩ conversion gain when driving 50-Ω output loads. Nested-feedback topologies are adopted for transimpedance and post limiting amplifier design to achieve broad-band and high-gain operations without shunt-peaking inductors. Implemented in a generic 40-nm CMOS technology, the chip size is 0.6 × 0.54 mm2. This receiver core drains 30 mW from 1-V supply.

KW - OEIC

KW - Optical Receiver

KW - Photo Detector (PD)

KW - Transimpedance Amplifier (TIA)

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U2 - 10.1109/ASSCC.2013.6691023

DO - 10.1109/ASSCC.2013.6691023

M3 - Conference contribution

AN - SCOPUS:84893613334

SN - 9781479902781

T3 - Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

SP - 225

EP - 228

BT - Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

T2 - 2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

Y2 - 11 November 2013 through 13 November 2013

ER -

A 20-Gb/s optical receiver with integrated photo detector in 40-nm CMOS

摘要

出版系列

Conference

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