A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-μm digital CMOS process

Wei-Zen Chen; Jia Xian Chang; Ying Jen Hong; Meng Tzer Wong; Chien Liang Kuo

doi:10.1109/JSSC.2003.820878

A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-μm digital CMOS process

Wei-Zen Chen^*, Jia Xian Chang, Ying Jen Hong, Meng Tzer Wong, Chien Liang Kuo

^*此作品的通信作者

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

摘要

This brief describes the design of a frequency synthesizer for 2.3/4.6-GHz wireless applications in a 0.35-μm digital CMOS process. This synthesizer provides dual-band output signals by means of frequency doubling techniques. Output frequency of the proposed synthesizer ranges from 1.87-2.3 GHz, and 3.74-4.6 GHz. This chip consumes a total power of 80 mW from a single 2-V supply, including 45 mW for dual-band output buffers. Core size is 2200 μm × 1600 μm.

原文	English
頁（從 - 到）	234-237
頁數	4
期刊	IEEE Journal of Solid-State Circuits
卷	39
發行號	1
DOIs	https://doi.org/10.1109/JSSC.2003.820878
出版狀態	Published - 1 1月 2004

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10.1109/JSSC.2003.820878

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@article{18743726a3084e9c920baea18aa4c9df,

title = "A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-μm digital CMOS process",

abstract = "This brief describes the design of a frequency synthesizer for 2.3/4.6-GHz wireless applications in a 0.35-μm digital CMOS process. This synthesizer provides dual-band output signals by means of frequency doubling techniques. Output frequency of the proposed synthesizer ranges from 1.87-2.3 GHz, and 3.74-4.6 GHz. This chip consumes a total power of 80 mW from a single 2-V supply, including 45 mW for dual-band output buffers. Core size is 2200 μm × 1600 μm.",

keywords = "Dual band, Frequency doubler, Frequency synthesizer",

author = "Wei-Zen Chen and Chang, {Jia Xian} and Hong, {Ying Jen} and Wong, {Meng Tzer} and Kuo, {Chien Liang}",

year = "2004",

month = jan,

day = "1",

doi = "10.1109/JSSC.2003.820878",

language = "English",

volume = "39",

pages = "234--237",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-μm digital CMOS process

AU - Chen, Wei-Zen

AU - Chang, Jia Xian

AU - Hong, Ying Jen

AU - Wong, Meng Tzer

AU - Kuo, Chien Liang

PY - 2004/1/1

Y1 - 2004/1/1

N2 - This brief describes the design of a frequency synthesizer for 2.3/4.6-GHz wireless applications in a 0.35-μm digital CMOS process. This synthesizer provides dual-band output signals by means of frequency doubling techniques. Output frequency of the proposed synthesizer ranges from 1.87-2.3 GHz, and 3.74-4.6 GHz. This chip consumes a total power of 80 mW from a single 2-V supply, including 45 mW for dual-band output buffers. Core size is 2200 μm × 1600 μm.

AB - This brief describes the design of a frequency synthesizer for 2.3/4.6-GHz wireless applications in a 0.35-μm digital CMOS process. This synthesizer provides dual-band output signals by means of frequency doubling techniques. Output frequency of the proposed synthesizer ranges from 1.87-2.3 GHz, and 3.74-4.6 GHz. This chip consumes a total power of 80 mW from a single 2-V supply, including 45 mW for dual-band output buffers. Core size is 2200 μm × 1600 μm.

KW - Dual band

KW - Frequency doubler

KW - Frequency synthesizer

UR - http://www.scopus.com/inward/record.url?scp=0742303641&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2003.820878

DO - 10.1109/JSSC.2003.820878

M3 - Article

AN - SCOPUS:0742303641

SN - 0018-9200

VL - 39

SP - 234

EP - 237

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 1

ER -

A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-μm digital CMOS process

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