@inproceedings{379ada98a67b429eba950faf00d8805f,
title = "A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS",
abstract = "This paper describes a single-chip, 2 × 20-Gb/s time-interleaved integrating-type optical receiver. Combining with correlation-based timing recovery and 1:4 demultiplexer, it achieves a high energy efficiency of 1.2-pJ/bit. By incorporating the proposed alternating photodetector (ALPD) current-sensing scheme, the front-end receiver is 4-way time-interleaved to increase input sensitivity and relax operating speed of digital comparator. The optical receiver achieves an input sensitivity of 44 μApp at bit-error-rate of less than 10-12. Fabricated in a 40-nm bulk CMOS technology, the chip size is 0.46 mm2.",
keywords = "Monolithic optical receiver, comparator, high-density optical interconnect, photodetector (PD)",
author = "Huang, {Shih Hao} and Hung, {Zheng Hao} and Chen, {Wei Zen}",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 ; Conference date: 10-11-2014 Through 12-11-2014",
year = "2015",
month = jan,
day = "13",
doi = "10.1109/ASSCC.2014.7008869",
language = "English",
series = "2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "97--100",
booktitle = "2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers",
address = "United States",
}
