A 188-size 2.1mm2 reconfigurable turbo decoder chip with parallel architecture for 3GPP LTE system

Cheng Chi Wong; Yung Yu Lee; Hsie-Chia Chang

A 188-size 2.1mm2 reconfigurable turbo decoder chip with parallel architecture for 3GPP LTE system

Cheng Chi Wong^*, Yung Yu Lee, Hsie-Chia Chang

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

36 引文斯高帕斯（Scopus）

摘要

This paper presents a turbo decoder chip supporting all 188 block sizes in 3GPP LTE standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block size, and the number of iteration can be adjusted. Moreover, a threestage network is utilized to connect multiple memory modules and multiple SISO decoders. After fabricated in 90nm process, the 2.1mm² chip can achieve 129Mb/s with 219mW for the 6144-bit block after 8 iterations.

原文	English
主出版物標題	2009 Symposium on VLSI Circuits
章節	28-2
頁面	288-289
頁數	2
出版狀態	Published - 16 6月 2009
事件	2009 Symposium on VLSI Circuits - Kyoto, Japan 持續時間: 16 6月 2009 → 18 6月 2009

出版系列

名字	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	2009 Symposium on VLSI Circuits
國家/地區	Japan
城市	Kyoto
期間	16/06/09 → 18/06/09

其它文件與鏈接

Link to publication in Scopus

引用此

@inproceedings{cf565c11f16a453ca81374d0f0f174b4,

title = "A 188-size 2.1mm2 reconfigurable turbo decoder chip with parallel architecture for 3GPP LTE system",

abstract = "This paper presents a turbo decoder chip supporting all 188 block sizes in 3GPP LTE standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block size, and the number of iteration can be adjusted. Moreover, a threestage network is utilized to connect multiple memory modules and multiple SISO decoders. After fabricated in 90nm process, the 2.1mm2 chip can achieve 129Mb/s with 219mW for the 6144-bit block after 8 iterations.",

keywords = "3GPP LTE, And QPP interleaver, Turbo decoder",

author = "Wong, {Cheng Chi} and Lee, {Yung Yu} and Hsie-Chia Chang",

year = "2009",

month = jun,

day = "16",

language = "English",

isbn = "9784863480018",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "288--289",

booktitle = "2009 Symposium on VLSI Circuits",

note = "2009 Symposium on VLSI Circuits ; Conference date: 16-06-2009 Through 18-06-2009",

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AU - Wong, Cheng Chi

AU - Lee, Yung Yu

AU - Chang, Hsie-Chia

PY - 2009/6/16

Y1 - 2009/6/16

N2 - This paper presents a turbo decoder chip supporting all 188 block sizes in 3GPP LTE standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block size, and the number of iteration can be adjusted. Moreover, a threestage network is utilized to connect multiple memory modules and multiple SISO decoders. After fabricated in 90nm process, the 2.1mm2 chip can achieve 129Mb/s with 219mW for the 6144-bit block after 8 iterations.

AB - This paper presents a turbo decoder chip supporting all 188 block sizes in 3GPP LTE standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block size, and the number of iteration can be adjusted. Moreover, a threestage network is utilized to connect multiple memory modules and multiple SISO decoders. After fabricated in 90nm process, the 2.1mm2 chip can achieve 129Mb/s with 219mW for the 6144-bit block after 8 iterations.

KW - 3GPP LTE

KW - And QPP interleaver

KW - Turbo decoder

UR - http://www.scopus.com/inward/record.url?scp=70449382446&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:70449382446

SN - 9784863480018

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 288

EP - 289

BT - 2009 Symposium on VLSI Circuits

T2 - 2009 Symposium on VLSI Circuits

Y2 - 16 June 2009 through 18 June 2009

ER -

A 188-size 2.1mm2 reconfigurable turbo decoder chip with parallel architecture for 3GPP LTE system

摘要

出版系列

Conference

其它文件與鏈接

指紋

引用此