A 188-Length Full Code Rate 333Mbps 1.08mm2 Radix-4 Hybrid-Trellis Turbo Decoder with Zero Patching for 3GPP LTE-A

Po Hsun Chang, Chen Yang Lin, Chia Hsiang Sun, Yen Chin Liao, Hsie-Chia Chang

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

Decoding high code rate Turbo codes by their reciprocal dual trellis has been shown to be potentially beneficial in implementation due to the simpler trellis structures. However, reciprocal dual trellis decoders' complexity grows significantly when the code rate is less than 1/2. Further, designing a multicode rate reciprocal dual trellis decoder is even more challenging if periodical puncturing patterns is not always available. In this paper, a radix-4 hybrid-trellis LTE-A turbo decoder with a controller switching between the conventional trellis and the reciprocal dual trellis is presented. To accommodate all the rates defined in LTE-A, a zero patching scheme is proposed to create the periodical puncturing patterns required by the reciprocal dual trellis decoding. The implementation of the proposed decoder supports all the code rates, from 1/3 to 0.95, and all the 188 block lengths. Fabricated in TSMC TN28HPM process, the post-layout simulations show the proposed decoder could achieve 333Mbps at 6 iterations under 263MHz operating frequency. The core area is 1.08 mm2, and the decoder draws 295.57 mW of power with energy efficiency of 0.148(nJ/bit/iter).

原文English
主出版物標題2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781538648810
DOIs
出版狀態Published - 26 4月 2018
事件2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy
持續時間: 27 5月 201830 5月 2018

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
2018-May
ISSN(列印)0271-4310

Conference

Conference2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
國家/地區Italy
城市Florence
期間27/05/1830/05/18

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