A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS

Fang Ju Ku; Tung Yu Wu; Yen Chin Liao; Hsie-Chia Chang; Wing Hung Wong; Chen-Yi Lee

doi:10.1109/VLSI-DAT.2018.8373265

A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS

Fang Ju Ku, Tung Yu Wu, Yen Chin Liao, Hsie-Chia Chang, Wing Hung Wong, Chen-Yi Lee

研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

This paper presents an implementation of an energy efficient bit-plane payload design for machine learning processor. The proposed architecture facilitates high parallelism and high data bandwidth and thus improves the model learning/training time of machine learning algorithms. By assembling multiple bits as a bit-plane and enlarging query parallelism with a central compare-flag updater, data processing parallelism can be increased. Binary sequential partition (BSP), a fast density estimation algorithm capable of dealing with high dimensional data sets, is realized. Fabricated in 90nm 1P9M CMOS process, the processing rate can achieve 16.9 Gb/sec with 8 queries for data dimension D=210. The test chip integrates 64 counting cells and provides 5 modes with power consumptions of 1.86mJ/Gb per Query.

原文	English
主出版物標題	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	1-4
頁數	4
ISBN（電子）	9781538642603
DOIs	https://doi.org/10.1109/VLSI-DAT.2018.8373265
出版狀態	Published - 5 6月 2018
事件	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan 持續時間: 16 4月 2018 → 19 4月 2018

出版系列

名字	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

Conference

Conference	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
國家/地區	Taiwan
城市	Hsinchu
期間	16/04/18 → 19/04/18

存取文件

10.1109/VLSI-DAT.2018.8373265

其它文件與鏈接

Link to publication in Scopus

引用此

Ku, F. J., Wu, T. Y., Liao, Y. C., Chang, H.-C., Wong, W. H., & Lee, C.-Y. (2018). A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS. 於 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 (頁 1-4). (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2018.8373265

@inproceedings{710f9315e93249a1b12a14a287f4391d,

title = "A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS",

abstract = "This paper presents an implementation of an energy efficient bit-plane payload design for machine learning processor. The proposed architecture facilitates high parallelism and high data bandwidth and thus improves the model learning/training time of machine learning algorithms. By assembling multiple bits as a bit-plane and enlarging query parallelism with a central compare-flag updater, data processing parallelism can be increased. Binary sequential partition (BSP), a fast density estimation algorithm capable of dealing with high dimensional data sets, is realized. Fabricated in 90nm 1P9M CMOS process, the processing rate can achieve 16.9 Gb/sec with 8 queries for data dimension D=210. The test chip integrates 64 counting cells and provides 5 modes with power consumptions of 1.86mJ/Gb per Query.",

keywords = "Bayesian sequential partition, big data analysis, bit-plane, hardware architecture",

author = "Ku, {Fang Ju} and Wu, {Tung Yu} and Liao, {Yen Chin} and Hsie-Chia Chang and Wong, {Wing Hung} and Chen-Yi Lee",

year = "2018",

month = jun,

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doi = "10.1109/VLSI-DAT.2018.8373265",

language = "English",

series = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--4",

booktitle = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018",

address = "United States",

note = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 ; Conference date: 16-04-2018 Through 19-04-2018",

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Ku, FJ, Wu, TY, Liao, YC, Chang, H-C, Wong, WH & Lee, C-Y 2018, A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS. 於 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, Institute of Electrical and Electronics Engineers Inc., 頁 1-4, 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, Hsinchu, Taiwan, 16/04/18. https://doi.org/10.1109/VLSI-DAT.2018.8373265

A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS. / Ku, Fang Ju; Wu, Tung Yu; Liao, Yen Chin 等.
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4 (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018).

研究成果: Conference contribution › 同行評審

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AU - Lee, Chen-Yi

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N2 - This paper presents an implementation of an energy efficient bit-plane payload design for machine learning processor. The proposed architecture facilitates high parallelism and high data bandwidth and thus improves the model learning/training time of machine learning algorithms. By assembling multiple bits as a bit-plane and enlarging query parallelism with a central compare-flag updater, data processing parallelism can be increased. Binary sequential partition (BSP), a fast density estimation algorithm capable of dealing with high dimensional data sets, is realized. Fabricated in 90nm 1P9M CMOS process, the processing rate can achieve 16.9 Gb/sec with 8 queries for data dimension D=210. The test chip integrates 64 counting cells and provides 5 modes with power consumptions of 1.86mJ/Gb per Query.

AB - This paper presents an implementation of an energy efficient bit-plane payload design for machine learning processor. The proposed architecture facilitates high parallelism and high data bandwidth and thus improves the model learning/training time of machine learning algorithms. By assembling multiple bits as a bit-plane and enlarging query parallelism with a central compare-flag updater, data processing parallelism can be increased. Binary sequential partition (BSP), a fast density estimation algorithm capable of dealing with high dimensional data sets, is realized. Fabricated in 90nm 1P9M CMOS process, the processing rate can achieve 16.9 Gb/sec with 8 queries for data dimension D=210. The test chip integrates 64 counting cells and provides 5 modes with power consumptions of 1.86mJ/Gb per Query.

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Ku FJ, Wu TY, Liao YC, Chang HC, Wong WH, Lee CY. A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS. 於 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-4. (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018). doi: 10.1109/VLSI-DAT.2018.8373265

A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS

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