A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

Wei-Zen Chen*, Ying Lien Cheng, Da Shin Lin


    研究成果: Article同行評審

    110 引文 斯高帕斯(Scopus)


    A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-μm CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV(PP). In order to avoid off-chip noise interference, the TIA and LA are de-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dBΩ and -3 dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12 dBm at a bit-error rate of 10-12 with a 231 -1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 μm × 1796 μm.

    頁(從 - 到)1388-1396
    期刊IEEE Journal of Solid-State Circuits
    出版狀態Published - 1 6月 2005


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