A 1.8-nW, -73.5-dB PSRR, 0.2-ms Startup Time, CMOS Voltage Reference with Self-Biased Feedback and Capacitively Coupled Schemes

Cheng Ze Shao, Shih Che Kuo, Yu Te Liao*

*此作品的通信作者

    研究成果: Article同行評審

    1 引文 斯高帕斯(Scopus)

    摘要

    This article presents a nanowatt CMOS voltage reference using self-biased and capacitively coupled schemes for improving the power supply rejection ratio (PSRR) and settling time without power-intensive auxiliary amplifiers and bias circuits. The chip was fabricated in a 0.18- $\mu \text{m}$ CMOS process. With the proposed schemes, the design can achieve a 1% settling time of 0.2 ms and a -73.5-dB PSRR at 100 Hz while only consuming 1.8 nW. The average temperature coefficient of 15 chips is 62 ppm/°C in a temperature range from -40 °C to 130 °C. The average voltage at 20 °C is 0.26 V, while the standard deviation is 1.1 mV and $3~\sigma $ accuracy is 0.43%.

    原文English
    文章編號9233942
    頁(從 - 到)1795-1804
    頁數10
    期刊IEEE Journal of Solid-State Circuits
    56
    發行號6
    DOIs
    出版狀態Published - 六月 2021

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