A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit

Po Chun Liu; Hsie-Chia Chang; Chen-Yi Lee

doi:10.1109/ESSCIRC.2009.5326020

A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit

Po Chun Liu^*, Hsie-Chia Chang, Chen-Yi Lee

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

20 引文斯高帕斯（Scopus）

摘要

The AES algorithm published in 2001 is now the most popular symmetric encryption algorithm. Several implementations have beed proposed but few of them considered the hardware cost and the throughput as a whole. This paper presents an AES core to be capable of both encryption and decryption with three different key lengths: 128-, 192-, and 256-bit. The overall hardware cost was optimized by a very compact on-the-fly key expansion unit and a highly integrated encryption/decryption datapath. The compact on-the-fly key expansion unit is achieved by sharing expansion processes of different key lengths. The integrated data datapath shares hardware resources between encryption and decryption. After manufactured in 90nm CMOS technology, the area of the chip is 15,577 equivalent gates with throughput up to 1.69 Gb/s operating at 131.8 MHz.

原文	English
主出版物標題	ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference
頁面	404-407
頁數	4
DOIs	https://doi.org/10.1109/ESSCIRC.2009.5326020
出版狀態	Published - 1 12月 2009
事件	35th European Solid-State Circuits Conference, ESSCIRC 2009 - Athens, 希臘持續時間: 14 9月 2009 → 18 9月 2009

出版系列

名字	ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference

Conference

Conference	35th European Solid-State Circuits Conference, ESSCIRC 2009
國家/地區	希臘
城市	Athens
期間	14/09/09 → 18/09/09

存取文件

10.1109/ESSCIRC.2009.5326020

其它文件與鏈接

Link to publication in Scopus

引用此

Liu, P. C., Chang, H.-C., & Lee, C.-Y. (2009). A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit. 於 ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference (頁 404-407). 文章 5326020 (ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2009.5326020

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title = "A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit",

abstract = "The AES algorithm published in 2001 is now the most popular symmetric encryption algorithm. Several implementations have beed proposed but few of them considered the hardware cost and the throughput as a whole. This paper presents an AES core to be capable of both encryption and decryption with three different key lengths: 128-, 192-, and 256-bit. The overall hardware cost was optimized by a very compact on-the-fly key expansion unit and a highly integrated encryption/decryption datapath. The compact on-the-fly key expansion unit is achieved by sharing expansion processes of different key lengths. The integrated data datapath shares hardware resources between encryption and decryption. After manufactured in 90nm CMOS technology, the area of the chip is 15,577 equivalent gates with throughput up to 1.69 Gb/s operating at 131.8 MHz.",

author = "Liu, {Po Chun} and Hsie-Chia Chang and Chen-Yi Lee",

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note = "35th European Solid-State Circuits Conference, ESSCIRC 2009 ; Conference date: 14-09-2009 Through 18-09-2009",

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Liu, PC, Chang, H-C & Lee, C-Y 2009, A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit. 於 ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference., 5326020, ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference, 頁 404-407, 35th European Solid-State Circuits Conference, ESSCIRC 2009, Athens, 希臘, 14/09/09. https://doi.org/10.1109/ESSCIRC.2009.5326020

A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit. / Liu, Po Chun; Chang, Hsie-Chia ; Lee, Chen-Yi.
ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference. 2009. p. 404-407 5326020 (ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference).

研究成果: Conference contribution › 同行評審

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A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit

摘要

出版系列

Conference

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其它文件與鏈接

指紋

引用此